V8R(Q=xlnx,versal-net-vnx-revAxlnx,versal-net-vnxxlnx,versal-net Xilinx Versal NET VNX revA ,=optionsu-bootu-boot,configJ cpus cpu-mapcluster0core0Zcore1Zcore2Zcore3Zcluster1core0Zcore1Zcore2Zcore3Z cluster2core0Z core1Z core2Z core3Z cluster3core0Zcore1Zcore2Zcore3Zcpu@0arm,cortex-a78^cpujpscix|@@ l2-cachecache@ cpu@100arm,cortex-a78^cpujpscix|@@ l2-cachecache@ cpu@200arm,cortex-a78^cpujpscix|@@ l2-cachecache@ cpu@300arm,cortex-a78^cpujpscix|@@ l2-cachecache@ cpu@10000arm,cortex-a78^cpujpscix|@@ l2-cachecache@ cpu@10100arm,cortex-a78^cpujpscix|@@ l2-cachecache@ cpu@10200arm,cortex-a78^cpujpscix|@@ l2-cachecache@ cpu@10300arm,cortex-a78^cpujpscix|@@ l2-cachecache@ cpu@20000arm,cortex-a78^cpujpscix|@@ l2-cachecache@ cpu@20100arm,cortex-a78^cpujpscix|@@  l2-cachecache@ cpu@20200arm,cortex-a78^cpujpscix|@@! l2-cachecache@ !cpu@20300arm,cortex-a78^cpujpscix|@@" l2-cachecache@ "cpu@30000arm,cortex-a78^cpujpscix|@@# l2-cachecache@$ #cpu@30100arm,cortex-a78^cpujpscix|@@% l2-cachecache@$ %cpu@30200arm,cortex-a78^cpujpscix|@@& l2-cachecache@$ &cpu@30300arm,cortex-a78^cpujpscix|@@' l2-cachecache@$ 'l3-0-cachecache @( l3-1-cachecache @( l3-2-cachecache @( l3-3-cachecache @( $l4-cachecache (idle-states+pscicpu-sleep-0arm,idle-state8@O`,qX' opp-tableoperating-points-v2 opp-1066000000?ހB@ opp-1866000000o8B@ opp-1900000000q?B@ opp-1999000000w&QB@ opp-2050000000z0B@ opp-2100000000}+uB@ opp-2200000000!VB@ opp-2400000000 B@ aliases/axi/serial@f1920000/axi/serial@f1930000/dcc/axi/mmc@f1040000/axi/mmc@f1050000/axi/i2c@f1940000/axi/i2c@f1950000/axi/rtc@f12a0000/axi/usb@f1e00000/axi/usb@f1e10000/axi/spi@f1010000/axi/spi@f1030000dccarm,dcc disabledfirmwarepsci arm,psci-1.0qsmcversal-net-firmware.xlnx,versal-net-firmwarexlnx,versal-firmwareqsmcfpga-region fpga-region) timerarm,armv8-timer0   versal-fpgaxlnx,versal-fpga )axi simple-bus "dma-controller@ebd00000xlnx,zynqmp-dma-1.0 disabledx H)clk_mainclk_apb5@@O**dma-controller@ebd10000xlnx,zynqmp-dma-1.0 disabledx I)clk_mainclk_apb5@@O**dma-controller@ebd20000xlnx,zynqmp-dma-1.0 disabledx J)clk_mainclk_apb5@@O**dma-controller@ebd30000xlnx,zynqmp-dma-1.0 disabledx K)clk_mainclk_apb5@@O**dma-controller@ebd40000xlnx,zynqmp-dma-1.0 disabledx L)clk_mainclk_apb5@@O**dma-controller@ebd50000xlnx,zynqmp-dma-1.0 disabledx M)clk_mainclk_apb5@@O**dma-controller@ebd60000xlnx,zynqmp-dma-1.0 disabledx N)clk_mainclk_apb5@@O**dma-controller@ebd70000xlnx,zynqmp-dma-1.0 disabledx O)clk_mainclk_apb5@@O**can@f1980000xlnx,canfd-2.0 disabledx` )can_clks_axi_aclkV@d O++can@f1990000xlnx,canfd-2.0 disabledx` )can_clks_axi_aclkV@d O++ethernet@f19e0000xlnx,versal-gemcdns,gem disabledx'' )pclkhclktx_clkrx_clktsu_clkO,,,,-ethernet@f19f0000xlnx,versal-gemcdns,gemokayx)) )pclkhclktx_clkrx_clktsu_clkO,,,,-u.5|/rmiimdio ethernet-phy@4x /interrupt-controller@e2000000 arm,gic-v3 x    " msi-controller@e2040000arm,gic-v3-itsxgpio@f19d0000xlnx,versal-gpio-1.0 disabledx O0gpio@f1020000xlnx,pmc-gpio-1.0 disabledx O0i2c@f1940000cdns,i2c-r1p14 disabledx  O0i2c@f1950000cdns,i2c-r1p14 disabledx  O0i3c@f1948000snps,dw-i3c-master-1.00a disabledx  O0i3c@f1958000snps,dw-i3c-master-1.00a disabledx  O0spi@f1010000#xlnx,versal-ospi-1.0cdns,qspi-nor disabled x   (O1=u.E spi@f1030000xlnx,versal-qspi-1.0 disabledx  )ref_clkpclkO22rtc@f12a0000xlnx,zynqmp-rtc disabledx* DalarmsecTmmc@f1040000#xlnx,versal-8.9aarasan,sdhci-8.9a disabledx )clk_xinclk_ahbgate`mclk_out_sd0clk_in_sd0 O113mmc@f1050000xlnx,versal-net-emmcokayx )clk_xinclk_ahbgate`mclk_out_sd1clk_in_sd1 O113u.CEserial@f1920000arm,pl011arm,primecell disabledx )uartclkapb_pclkO00serial@f1930000arm,pl011arm,primecellokayx )uartclkapb_pclkO00iommu@ec000000 arm,smmu-v3okayx Dcombined = .spi@f1960000cdns,spi-r1p6 disabled x )ref_clkpclkO11spi@f1970000cdns,spi-r1p6 disabled x )ref_clkpclkO11timer@f1dc0000 cdns,ttc disabled$+,- xO4timer@f1dd0000 cdns,ttc disabled$./0 xtimer@f1de0000 cdns,ttc disabled$123 xtimer@f1df0000 cdns,ttc disabled$456 xusb@f1e00000xlnx,versal-dwc3 disabledx)bus_clkref_clk" O55usb@f1b00000 snps,dwc3 disabledxDhostperipheralotgwakeup0!b