j8]\( ]$4mediatek,mt8395-evkmediatek,mt8395mediatek,mt8195 +"7MediaTek Genio 1200 EVK-P1V2-EMMCaliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/mailbox@10320000T/soc/mailbox@10330000Y/soc/hdr-engine@1c114000`/soc/mutex@1c016000g/soc/mutex@1c101000n/soc/vpp-merge@1c10c000u/soc/vpp-merge@1c10d000|/soc/vpp-merge@1c10e000/soc/vpp-merge@1c10f000/soc/vpp-merge@1c110000/soc/dma-controller@1c104000/soc/dma-controller@1c105000/soc/dma-controller@1c106000/soc/dma-controller@1c107000/soc/dma-controller@1c108000/soc/dma-controller@1c109000/soc/dma-controller@1c10a000/soc/dma-controller@1c10b000/soc/serial@11001100/soc/ethernet@11021000cpus+cpu@0cpuarm,cortex-a55 psci-ec3@=4P`m@@ cpu@100cpuarm,cortex-a55 psci-ec3@=4P`m@@ cpu@200cpuarm,cortex-a55 psci-ec3@=4P`m@@ cpu@300cpuarm,cortex-a55 psci-ec3@=4P`m@@ cpu@400cpuarm,cortex-a78 psci-f=P`m@@ cpu@500cpuarm,cortex-a78 psci-f=P`m@@cpu@600cpuarm,cortex-a78 psci-f=P`m@@cpu@700cpuarm,cortex-a78 psci-f=P`m@@cpu-mapcluster0core0 core1 core2 core3 core4 core5core6core7idle-statespscicpu-retention-larm,idle-state2*_:Dcpu-retention-barm,idle-state-*:cpu-off-larm,idle-state7*:Hcpu-off-barm,idle-state2*:l2-cache0cacheKbo@Wl2-cache1cacheKbo@Wl3-cachecacheKb o@Wdsu-pmu arm,dsu-pmue p ufaildmic-codec dmic-codec|mt8195-sounduokaymediatek,mt8195_mt6359 7mt8395-evkdefault,HeadphoneHeadphone LHeadphoneHeadphone Rheadphone-dai-link DL_SRC_BEcodecfixed-factor-clock-13mfixed-factor-clockclk13m-oscillator-26m fixed-clock-clk26moscillator-32k fixed-clock-clk32kperformance-controller@11bc10mediatek,cpufreq-hw  0 /opp-table-gpuoperating-points-v2Iopp-390000000T>[ hopp-410000000Tp[ opp-431000000T[ opp-473000000T1h@[ <opp-515000000TF[ <opp-556000000T!#[ Ҧopp-598000000T#[ opp-640000000T&%[ opp-670000000T'c[ opp-700000000T)'[ Lopp-730000000T+[ }opp-760000000T-L[ `opp-790000000T/q[ 4opp-820000000T05[ opp-850000000T2[ @opp-880000000T4s[ qpmu-a55arm,cortex-a55-pmu epmu-a78arm,cortex-a78-pmu epsci arm,psci-1.0smctimerarm,armv8-timer @e   soc+ simple-busipinterrupt-controller@c000000 arm,gic-v3{     e ppi-partitionsinterrupt-partition-0 interrupt-partition-1 syscon@10000000 mediatek,mt8195-topckgensysconsyscon@10001000#mediatek,mt8195-infracfg_aosysconsyscon@10003000mediatek,mt8195-pericfgsyscon0Ipinctrl@10005000mediatek,mt8195-pinctrlPBiocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleinte{audio-default-pinspins-cmd-dat4=>ABCDEFGHIJKdisp-pwm1-default-pinspins1hedp-panel-12v-en-pinspins1`edp-panel-3v3-en-pinspins1eth-default-pinsEpins-ccUVWXpins-mdioYZ"pins-power[\pins-rxdQRSTpins-txdMNOPeth-sleep-pinsFpins-ccUVWXpins-mdioYZ/=pins-rxdQRSTpins-txdMNOPgpio-keys-pinspinsjJ"i2c0-pinsjpins JWi2c1-pinskpins  JWi2c2-pinsnpins  Ji2c6-pinscpinsJmmc0-default-pinsNpins-clkzofpins-cmd-dat$~}|{wvuty"Jepins-rstxJemmc0-uhs-pinsOpins-clkzofpins-cmd-dat$~}|{wvuty"Jepins-dsofpins-rstxJemmc1-default-pinsRpins-clkoofpins-cmd-datnpqrs"Jemmc1-uhs-pinsSpins-clkoofpins-cmd-datnpqrs"Jemt6360-pinsdpins"Jdsi0-vreg-en-pinspins-pwr-en/~panel-default-pinspins-rstlpins-en0~pcie0-default-pins^pins Jpcie0-idle-pins_pins=~pcie1-default-pinsapins Jdisp-pwm0-pins<pins-disp-pwmaspi1-pins=pins=spi-pins@pins=touch-pinsmpins-irq"=pins-resetu3-p0-vbus-default-pinsJpins-vbus?"uart0-pins7pinsbcuart1-pins8pinsdefgsyscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfd`power-controller!mediatek,mt8195-power-controller+0power-domain@8+power-domain@9 mfgalt+power-domain@10 power-domain@11 power-domain@12 power-domain@13 power-domain@14power-domain@15 @AK   vppsysvppsys1vppsys2vppsys3vppsys4vppsys5vppsys6vppsys7vppsys0-0vppsys0-1vppsys0-2vppsys0-3vppsys0-4vppsys0-5vppsys0-6vppsys0-7vppsys0-8vppsys0-9vppsys0-10vppsys0-11vppsys0-12vppsys0-13vppsys0-14vppsys0-15vppsys0-16vppsys0-17vppsys0-18+power-domain@168 $ % & ' ( )Dvdosys0vdosys0-0vdosys0-1vdosys0-2vdosys0-3vdosys0-4vdosys0-5+power-domain@17!!vppsys1vppsys1-0vppsys1-1power-domain@22 """"$wepsys-0wepsys-1wepsys-2wepsys-3power-domain@23#vdec0-0+power-domain@24$vdec1-0power-domain@25%vdec2-0power-domain@26& venc0-larb+power-domain@27' venc1-larbpower-domain@18 (((&vdosys1vdosys1-0vdosys1-1vdosys1-2+power-domain@19power-domain@20power-domain@21Qhdmi_txpower-domain@28))  img-0img-1+power-domain@29power-domain@30)*ipeipe-0ipe-1power-domain@31(+++++cam-0cam-1cam-2cam-3cam-4+power-domain@32 power-domain@33!power-domain@34"power-domain@0power-domain@1power-domain@2power-domain@3power-domain@457csi_rx_topcsi_rx_top1power-domain@5, etherpower-domain@6Xn adspadsp1+power-domain@7 g"n2audioaudio1audio2audio3watchdog@10007000mediatek,mt8195-wdtp5syscon@1000c000"mediatek,mt8195-apmixedsyssyscontimer@10017000,mediatek,mt8195-timermediatek,mt6765-timerpe -pwrap@10024000mediatek,mt8195-pwrapsyscon@pwrape spiwrap$pmicmediatek,mt6359{ adcmediatek,mt6359-auxadc-audio-codecmediatek,mt6359-codec?Sgregulatorsmediatek,mt6359-regulatorbuck_vs1{vs1 5!buck_vgpu11{vgpu117 buck_vmodem{vmodem*buck_vpu{vpu7 buck_vcore{vcore  buck_vs2{vs2 5jbuck_vpa{vpa 7,buck_vproc2{vproc27L buck_vproc1{vproc17L buck_vcore_sshub {vcore_sshub7buck_vgpu11_sshub {vgpu11_sshub7ldo_vaud18{vaud18w@w@ldo_vsim1{vsim1/M`ldo_vibr{vibrO2Zoldo_vrf12{vrf12 ldo_vusb{vusb--Kldo_vsram_proc2 {vsram_proc2 Lldo_vio18{vio18ldo_vcamio{vcamioldo_vcn18{vcn18w@w@ldo_vfe28{vfe28**xldo_vcn13{vcn13  ldo_vcn33_1_bt {vcn33_1_bt*5gldo_vcn33_1_wifi {vcn33_1_wifi*5gldo_vaux18{vaux18w@w@ldo_vsram_others {vsram_others q qldo_vefuse{vefuseldo_vxo22{vxo22w@!ldo_vrfck{vrfck`ldo_vrfck_1{vrfckjldo_vbif28{vbif28**ldo_vio28{vio28*2Zldo_vemc{vemc,@ 2Zldo_vemc_1{vemc&%2ZPldo_vcn33_2_bt {vcn33_2_bt2Z2Z?ldo_vcn33_2_wifi {vcn33_2_wifi*5gldo_va12{va12O ldo_va09{va09 5Oldo_vrf18{vrf18Pldo_vsram_md {vsram_md *ldo_vufs{vufsQldo_vm18{vm18ldo_vbbck{vbbckOldo_vsram_proc1 {vsram_proc1 Lldo_vsim2{vsim2/M`ldo_vsram_others_sshub{vsram_others_sshub rtcmediatek,mt6358-rtckeysmediatek,mt6359-keys0power-keyCtRhomeCfspmi@10027000mediatek,mt8195-spmi p pmifspmimstE(pmif_sys_ckpmif_tmr_ckspmimst_clk_mux$+pmic@6mediatek,mt6315-regulatorregulatorsvbuck1{Vbcpu7 pmic@7mediatek,mt6315-regulatorregulatorsvbuck1{VgpuT 8 infra-iommu@10315000mediatek,mt8195-iommu-infra1PPPe`[mailbox@10320000mediatek,mt8195-gce2@emmailbox@10330000mediatek,mt8195-gce3@emscp@10500000mediatek,mt8195-scp0Prpsramcfgl1tcmeuokayy.mediatek/mt8195/scp.imgclock-controller@10720000mediatek,mt8195-scp_adspr/dsp@10803000mediatek,mt8195-dsp 0 cfgsram,Xn/#Kadsp_selclk26m_ckaudio_local_busmainpll_d7_d2scp_adsp_audiodspaudio_h0rxtx12uokayy34mailbox@10816000mediatek,mt8195-adsp-mboxm`e1mailbox@10817000mediatek,mt8195-adsp-mboxmpe2mt8195-afe-pcm@10890000mediatek,mt8195-audio0e65 audiosysg"#neabcd2/clk26mapll1_ckapll2_ckapll12_div0apll12_div1apll12_div2apll12_div3apll12_div9a1sys_hp_selaud_intbus_selaudio_h_selaudio_local_bus_seldptx_m_seli2so1_m_seli2so2_m_seli2si1_m_seli2si2_m_selinfra_ao_audio_26m_bscp_adsp_audiodspuokayy6serial@11001100*mediatek,mt8195-uartmediatek,mt6577-uarte  baudbusuokay7defaultserial@11001200*mediatek,mt8195-uartmediatek,mt6577-uarte  baudbusuokay8defaultserial@11001300*mediatek,mt8195-uartmediatek,mt6577-uarte  baudbus udisabledserial@11001400*mediatek,mt8195-uartmediatek,mt6577-uarte  baudbus udisabledserial@11001500*mediatek,mt8195-uartmediatek,mt6577-uarte  baudbus udisabledserial@11001600*mediatek,mt8195-uartmediatek,mt6577-uarte  baudbus udisabledauxadc@11002000.mediatek,mt8195-auxadcmediatek,mt8173-auxadc main- udisabledsyscon@11003000"mediatek,mt8195-pericfg_aosyscon0,spi@1100a000(mediatek,mt8195-spimediatek,mt6765-spi+eparent-clksel-clkspi-clk udisabledthermal-sensor@1100b000mediatek,mt8195-lvts-ap e9:$lvts-calib-data-1lvts-calib-data-2svs@1100bc00mediatek,mt8195-svsemain;9(svs-calibration-datat-calibration-datasvs_rstpwm@1100e0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwme0 *0mainmmuokaydefault<pwm@1100f0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwme +Nmainmm udisabledspi@11010000(mediatek,mt8195-spimediatek,mt6765-spi+e3parent-clksel-clkspi-clkuokay=default ,@can@0microchip,mcp2518fd>51- G?R?spi@11012000(mediatek,mt8195-spimediatek,mt6765-spi+ e4parent-clksel-clkspi-clkuokay@defaultspi@11013000(mediatek,mt8195-spimediatek,mt6765-spi+0e5parent-clksel-clkspi-clk udisabledspi@11018000(mediatek,mt8195-spimediatek,mt6765-spi+e<parent-clksel-clkspi-clk udisabledspi@11019000(mediatek,mt8195-spimediatek,mt6765-spi+e=parent-clksel-clkspi-clk udisabledspi@1101d000mediatek,mt8195-spi-slaveeRspi udisabledspi@1101e000mediatek,mt8195-spi-slaveeSspi udisabledethernet@11021000&mediatek,mt8195-gmacsnps,dwmac-5.10a@eamacirq.axiapbmac_mainptp_refrmii_internalmac_cg0,,RST, RST0qABCuokay rgmii-rxidD ] '')defaultsleepE:Fmdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-id001c.c916Dstmmac-axi-configDTdArx-queues-confignBqueue0queue1queue2queue3tx-queues-configCqueue0queue1queue2queue3usb@11201000#mediatek,mt8195-mtu3mediatek,mtu3  - > macippci ?+e/Bsys_ckref_ckmcu_ck GHR Iguokay otgdefaultJ & 6Kusb@0'mediatek,mt8195-xhcimediatek,mtk-xhcimace,-$/B$sys_ckref_ckmcu_ckdma_ckxhci_ckuokayports+port@0endpoint DLfport@1endpoint DMgmmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc #esourcehclksource_cguokaydefaultstate_uhsN:O T9  ^ p     L P Q mmc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc $e$sourcehclksource_cguokaydefaultstate_uhsR:S T9       T U mmc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc %e Isourcehclksource_cg  udisabledufshci@11270000mediatek,mt8195-ufshci'#e V@?@A678Z]Xufsufs_aesufs_tickunipro_sysclkunipro_tickunipro_mp_bclkufs_tx_symbolufs_mem_sub@  $ udisabledthermal-sensor@11278000mediatek,mt8195-lvts-mcu'e9:$lvts-calib-data-1lvts-calib-data-2usb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci ))> macippce WX./$,,$sys_ckref_ckmcu_ckdma_ckxhci_ck IhRuokay 6Kusb@112a1000#mediatek,mt8195-mtu3mediatek,mtu3 *-*> macippci*?+e0,,sys_ckref_ckmcu_ck YR Iiuokay 6Kusb@0'mediatek,mt8195-xhcimediatek,mtk-xhcimace1,sys_ckuokayusb@112b1000#mediatek,mt8195-mtu3mediatek,mtu3 +-+> macippci+?+e2,, sys_ckref_ckmcu_ck ZR Ijuokay 6Kusb@0'mediatek,mt8195-xhcimediatek,mtk-xhcimace3, sys_ckuokaypcie@112f0000*mediatek,mt8195-pciemediatek,mt8192-pciepci+/@ pcie-mace =8i  G[ Q0V#&+K,/pl_250mtl_26mtl_96mtl_32kperi_26mperi_memG \ `pcie-phy0{ j` }]]]]uokay defaultidle^:_interrupt-controller{]pcie@112f8000*mediatek,mt8195-pciemediatek,mt8192-pciepci+/@ pcie-mace =8i$$ $ $  G[ Q(WXQ,/pl_250mtl_26mtl_96mtl_32kperi_26mperi_memH X `pcie-phy0{ j` }```` udisableddefaultainterrupt-controller{`spi@1132c000(mediatek,mt8195-normediatek,mt8173-nor2e9o,, spisfaxi+ udisabledefuse@11c10000%mediatek,mt8195-efusemediatek,efuse+usb3-tx-imp@184,1 vusb3-rx-imp@184,2 uusb3-intr@185 tusb3-tx-imp@186,1 susb3-rx-imp@186,2 rusb3-intr@187 qusb2-intr-p0@188,1 usb2-intr-p1@188,2 usb2-intr-p2@189,1 usb2-intr-p3@189,2 pciephy-rx-ln1@190,1 }pciephy-tx-ln1-nmos@190,2 |pciephy-tx-ln1-pmos@191,1 {pciephy-rx-ln0@191,2 zpciephy-tx-ln0-nmos@192,1 ypciephy-tx-ln0-pmos@192,2 xpciephy-glb-intr@193 wdp-data@1aclvts1-calib@1bc9lvts2-calib@1d08:svs-calib@580d;socinfo-data1@7a0t-phy@11c40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+iuokayusb-phy@0ref Yt-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+iuokayusb-phy@0ref Zdsi-phy@11c800000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx mipi_tx0_pll uokaydsi-phy@11c900000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx mipi_tx1_pll  udisabledi2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c "eb; maindma+ udisabledi2c@11d01000(mediatek,mt8195-i2cmediatek,mt8192-i2c "eb; maindma+uokay-cdefaultpmic@34mediatek,mt63604 eaIRQB{dchargermediatek,mt6360-chg @usb-otg-vbus-regulator {usb-otg-vbusC(Xregulatormediatek,mt6360-regulator ebuck1 {emi_vdd2  buck2 {emi_vddq  eldo1 {tp1_p3v02Z2Zlldo2 {panel1_p1v8w@w@ldo3{vmc_pmuO6Uldo5 {vmch_pmu)26Tldo6 {mt6360_ldo1  ldo7 {emi_vmddr_en  tcpcmediatek,mt6360-tcpc aPD_IRQBconnectorusb-c-connector USB-C dual  dual sink "d " altmodesdisplayport " 'Fports+port@0endpoint DfLport@1endpoint DgMport@2endpoint Dhpi2c@11d02000(mediatek,mt8195-i2cmediatek,mt8192-i2c  "eb; maindma+ udisabledclock-controller@11d03000mediatek,mt8195-imp_iic_wrap_s0bi2c@11e00000(mediatek,mt8195-i2cmediatek,mt8192-i2c "ei; maindma+uokay-jdefaulti2c@11e01000(mediatek,mt8195-i2cmediatek,mt8192-i2c "ei; maindma+uokay-kdefaulttouchscreen@5dgoodix,gt9271]  + 5 Aldefaultmi2c@11e02000(mediatek,mt8195-i2cmediatek,mt8192-i2c  "ei; maindma+uokay-ndefaulttypec-mux@48 ite,it5205H Oo Z fuokayportendpoint Dphi2c@11e03000(mediatek,mt8195-i2cmediatek,mt8192-i2c 0"ei; maindma+ udisabledi2c@11e04000(mediatek,mt8195-i2cmediatek,mt8192-i2c @"ei; maindma+ udisabledclock-controller@11e05000mediatek,mt8195-imp_iic_wrap_wPit-phy@11e30000.mediatek,mt8195-tphymediatek,generic-tphy-v3+i0uokayusb-phy@0  refda_ref Wusb-phy@700 refda_ref qrsintrrx_imptx_imp  yXt-phy@11e40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+iuokayusb-phy@0  refda_ref Gusb-phy@700 refda_ref tuvintrrx_imptx_imp Hphy@11e80000mediatek,mt8195-pcie-physifwxyz{|}Gglb_intrtx_ln0_pmostx_ln0_nmosrx_ln0tx_ln1_pmostx_ln1_nmosrx_ln10 uokay\ufs-phy@11fa0000.mediatek,mt8195-ufsphymediatek,mt8183-ufsphy unipromp  udisabledVgpu@13000000>mediatek,mt8195-malimediatek,mt8192-maliarm,mali-valhall-jm@~0e ajobmmugpu (0 0 0 0 0 core0core1core2core3core4uokay clock-controller@13fbf000mediatek,mt8195-mfgcfg~syscon@14000000mediatek,mt8195-vppsys0syscon dma-controller@14001000mediatek,mt8195-mdp3-rdma    0 <   display@14002000mediatek,mt8195-mdp3-fg  display@14003000mediatek,mt8195-mdp3-stitch0 0display@14004000mediatek,mt8195-mdp3-hdr@ @"display@14005000mediatek,mt8195-mdp3-aalPeF P 0display@140060002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz` ` % display@14007000mediatek,mt8195-mdp3-tdshpp p#display@14008000mediatek,mt8195-mdp3-coloreI $0display@14009000mediatek,mt8195-mdp3-ovleJ %0 display@1400a000mediatek,mt8195-mdp3-padding 0display@1400b000mediatek,mt8195-mdp3-tcc dma-controller@1400c0004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot   + 0 mutex@1400f000mediatek,mt8195-vpp-mutexeP 0smi@14010000mediatek,mt8195-smi-sub-commonapbsmigals0 0smi@14011000mediatek,mt8195-smi-sub-commonapbsmigals0 0smi@14012000mediatek,mt8195-smi-common-vpp  apbsmigals0gals10larb@14013000mediatek,mt8195-smi-larb0  apbsmi0iommu@14018000mediatek,mt8195-iommu-vpp8 )eRbclk`0clock-controller@14e00000mediatek,mt8195-wpesys"clock-controller@14e02000mediatek,mt8195-wpesys_vpp0 clock-controller@14e03000mediatek,mt8195-wpesys_vpp10larb@14e04000mediatek,mt8195-smi-larb@  ""apbsmi0larb@14e05000mediatek,mt8195-smi-larbP  "" apbsmigals0syscon@14f00000mediatek,mt8195-vppsys1syscon !mutex@14f01000mediatek,mt8195-vpp-mutexe{ !'0larb@14f02000mediatek,mt8195-smi-larb   !! apbsmigals0larb@14f03000mediatek,mt8195-smi-larb0  !! apbsmigals0display@14f06000mediatek,mt8195-mdp3-split` `!!+!,0display@14f07000mediatek,mt8195-mdp3-tccp p!dma-controller@14f08000mediatek,mt8195-mdp3-rdma  ! 0 dma-controller@14f09000mediatek,mt8195-mdp3-rdma  !  0 dma-controller@14f0a000mediatek,mt8195-mdp3-rdma  !  0 display@14f0b000mediatek,mt8195-mdp3-fg ! display@14f0c000mediatek,mt8195-mdp3-fg ! display@14f0d000mediatek,mt8195-mdp3-fg ! display@14f0e000mediatek,mt8195-mdp3-hdr !display@14f0f000mediatek,mt8195-mdp3-hdr !display@14f10000mediatek,mt8195-mdp3-hdr ! display@14f11000mediatek,mt8195-mdp3-aalei !0display@14f12000mediatek,mt8195-mdp3-aal ej !0display@14f13000mediatek,mt8195-mdp3-aal0ek 0!!0display@14f140002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz@ @ !display@14f150002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rszP P !$display@14f160002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz` ` !%display@14f17000mediatek,mt8195-mdp3-tdshpp p!display@14f18000mediatek,mt8195-mdp3-tdshp !(display@14f19000mediatek,mt8195-mdp3-tdshp !)display@14f1a000mediatek,mt8195-mdp3-merge !0display@14f1b000mediatek,mt8195-mdp3-merge !0display@14f1c000mediatek,mt8195-mdp3-coloret !0display@14f1d000mediatek,mt8195-mdp3-color eu!0display@14f1e000mediatek,mt8195-mdp3-colorev !0display@14f1f000mediatek,mt8195-mdp3-ovlew !0 display@14f20000mediatek,mt8195-mdp3-padding !0display@14f21000mediatek,mt8195-mdp3-padding !0display@14f22000mediatek,mt8195-mdp3-padding  !0dma-controller@14f230004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot0 0 ! 0 dma-controller@14f240004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot@ @ ! 0 dma-controller@14f250004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrotP P ! 0 clock-controller@15000000mediatek,mt8195-imgsys)larb@15001000mediatek,mt8195-smi-larb   )))  apbsmigals0smi@15002000mediatek,mt8195-smi-sub-common ))apbsmigals0 0smi@15003000mediatek,mt8195-smi-sub-common0))) apbsmigals0 0clock-controller@15110000 mediatek,mt8195-imgsys1_dip_toplarb@15120000mediatek,mt8195-smi-larb   )apbsmi0clock-controller@15130000mediatek,mt8195-imgsys1_dip_nrclock-controller@15220000mediatek,mt8195-imgsys1_wpe"larb@15230000mediatek,mt8195-smi-larb#   )apbsmi0clock-controller@15330000mediatek,mt8195-ipesys3*larb@15340000mediatek,mt8195-smi-larb4   **apbsmi0clock-controller@16000000mediatek,mt8195-camsys+larb@16001000mediatek,mt8195-smi-larb   +++ apbsmigals0larb@16002000mediatek,mt8195-smi-larb   ++apbsmi0smi@16004000mediatek,mt8195-smi-sub-common@+++apbsmigals0 0smi@16005000mediatek,mt8195-smi-sub-commonP++apbsmigals0 0larb@16012000mediatek,mt8195-smi-larb   apbsmi0 larb@16013000mediatek,mt8195-smi-larb0  apbsmi0 larb@16014000mediatek,mt8195-smi-larb@  apbsmi0!larb@16015000mediatek,mt8195-smi-larbP  apbsmi0!clock-controller@1604f000mediatek,mt8195-camsys_rawaclock-controller@1606f000mediatek,mt8195-camsys_yuvaclock-controller@1608f000mediatek,mt8195-camsys_rawbclock-controller@160af000mediatek,mt8195-camsys_yuvb clock-controller@16140000mediatek,mt8195-camsys_mrawlarb@16141000mediatek,mt8195-smi-larb  ++ apbsmigals0"larb@16142000mediatek,mt8195-smi-larb   apbsmi0"clock-controller@17200000mediatek,mt8195-ccusys larb@17201000mediatek,mt8195-smi-larb   apbsmi0video-codec@18000000mediatek,mt8195-vcodec-dec  + @i`video-codec@2000mediatek,mtk-vcodec-lat-soc   A##selvdeclattopA0video-codec@10000mediatek,mtk-vcodec-late0  A##selvdeclattopA0video-codec@25000mediatek,mtk-vcodec-corePeP  A$$selvdeclattopA0larb@1800d000mediatek,mt8195-smi-larb  ##apbsmi0larb@1800e000mediatek,mt8195-smi-larb  #apbsmi0clock-controller@1800f000mediatek,mt8195-vdecsys_soc#larb@1802e000mediatek,mt8195-smi-larb  $$apbsmi0clock-controller@1802f000mediatek,mt8195-vdecsys$larb@1803e000mediatek,mt8195-smi-larb  %apbsmi0clock-controller@1803f000mediatek,mt8195-vdecsys_core1%clock-controller@190f3000mediatek,mt8195-apusys_pll0clock-controller@1a000000mediatek,mt8195-vencsys&larb@1a010000mediatek,mt8195-smi-larb  &&apbsmi0video-codec@1a020000mediatek,mt8195-vcodec-encH `abcdvwxyeU & venc_sel@0+jpeg-decoder@1a040000mediatek,mt8195-jpgdec00 mnrstu+0ijpgdec@0,0mediatek,mt8195-jpgdec-hw0 mnrstueW&jpgdec0jpgdec@0,10000mediatek,mt8195-jpgdec-hw0 mnrstueX&jpgdec0jpgdec@1,0mediatek,mt8195-jpgdec-hw0 e\'jpgdec0clock-controller@1b000000mediatek,mt8195-vencsys_core1'syscon@1c01a0005mediatek,mt8195-vdosys0mediatek,mt8195-mmsyssyscon   port+endpoint@0 Djpeg-encoder@1a030000mediatek,mt8195-jpgenc0 +0ijpgenc@0,0mediatek,mt8195-jpgenc-hw ghileV&jpgenc0jpgenc@1,0mediatek,mt8195-jpgenc-hw e['jpgenc0larb@1b010000mediatek,mt8195-smi-larb  ''  apbsmigals0ovl@1c000000mediatek,mt8195-disp-ovle|0   ports+port@0endpoint Dport@1endpoint Drdma@1c002000mediatek,mt8195-disp-rdma e~0    ports+port@0endpoint Dport@1endpoint Dcolor@1c0030006mediatek,mt8195-disp-colormediatek,mt8173-disp-color0e0  0ports+port@0endpoint Dport@1endpoint Dccorr@1c0040006mediatek,mt8195-disp-ccorrmediatek,mt8192-disp-ccorr@e0  @ports+port@0endpoint Dport@1endpoint Daal@1c0050002mediatek,mt8195-disp-aalmediatek,mt8183-disp-aalPe0  Pports+port@0endpoint Dport@1endpoint Dgamma@1c0060006mediatek,mt8195-disp-gammamediatek,mt8183-disp-gamma`e0  `ports+port@0endpoint Dport@1endpoint Ddither@1c0070008mediatek,mt8195-disp-dithermediatek,mt8183-disp-ditherpe0  pports+port@0endpoint Dport@1endpoint Ddsi@1c008000(mediatek,mt8195-dsimediatek,mt8183-dsie0  *enginedigitalhs  `dphyuokay+panel@0#startek,kd070fhfid078himax,hx8279 8 B0 5l OGdefaultportendpoint Dports+port@0endpoint Dport@1endpoint Ddsc@1c009000mediatek,mt8195-disp-dsce0  dsi@1c012000(mediatek,mt8195-dsimediatek,mt8183-dsi e0  +enginedigitalhs  `dphy udisabledmerge@1c014000mediatek,mt8195-disp-merge@e0  @dp-intf@1c015000mediatek,mt8195-dp-intfPe0 , pixelenginepll udisabledmutex@1c016000mediatek,mt8195-disp-mutex`e0  ` Ularb@1c018000mediatek,mt8195-smi-larb   ( (  apbsmigals0larb@1c019000mediatek,mt8195-smi-larb   (  apbsmigals0syscon@1c100000mediatek,mt8195-vdosys1syscon  (smi@1c01b000mediatek,mt8195-smi-common-vdo  % & ) $apbsmigals0gals10iommu@1c01f000mediatek,mt8195-iommu-vdo8 )e` 'bclk0mutex@1c101000mediatek,mt8195-disp-mutexe0(  larb@1c102000mediatek,mt8195-smi-larb   ((( apbsmigals0larb@1c103000mediatek,mt8195-smi-larb0  ((  apbsmigals0dma-controller@1c104000mediatek,mt8195-vdo1-rdma@e(0 @ @ dma-controller@1c105000mediatek,mt8195-vdo1-rdmaPe(0 ` P dma-controller@1c106000mediatek,mt8195-vdo1-rdma`e(0 A ` dma-controller@1c107000mediatek,mt8195-vdo1-rdmape(0 a p dma-controller@1c108000mediatek,mt8195-vdo1-rdmae(0 B  dma-controller@1c109000mediatek,mt8195-vdo1-rdmae(0 b  dma-controller@1c10a000mediatek,mt8195-vdo1-rdmae(0 C  dma-controller@1c10b000mediatek,mt8195-vdo1-rdmae(0 c  vpp-merge@1c10c000mediatek,mt8195-disp-mergee( (mergemerge_async0  \(vpp-merge@1c10d000mediatek,mt8195-disp-mergee( (mergemerge_async0  \(vpp-merge@1c10e000mediatek,mt8195-disp-mergee( (mergemerge_async0  \(vpp-merge@1c10f000mediatek,mt8195-disp-mergee( (mergemerge_async0  \(vpp-merge@1c110000mediatek,mt8195-disp-mergee( (mergemerge_async0  p(dp-intf@1c113000mediatek,mt8195-dp-intf0e0(/(pixelenginepll udisabledhdr-engine@1c114000mediatek,mt8195-disp-ethdrp@Pp4mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsp @Pph(%( (#(!($("(1(&('((()(*mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top0 dee((3(4(5(6(7Evdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncedp-tx@1c500000mediatek,mt8195-edp-txPdp_calibration_data0e  udisableddp-tx@1c600000mediatek,mt8195-dp-tx`dp_calibration_data0e  udisabledthermal-zonescpu0-thermal   tripstrip-alert L passivetrip-crit   criticalcooling-mapsmap0 0 cpu1-thermal   tripstrip-alert L passivetrip-crit   criticalcooling-mapsmap0 0 cpu2-thermal   tripstrip-alert L passivetrip-crit   criticalcooling-mapsmap0 0 cpu3-thermal   tripstrip-alert L passivetrip-crit   criticalcooling-mapsmap0 0 cpu4-thermal   tripstrip-alert L passivetrip-crit   criticalcooling-mapsmap0 0 cpu5-thermal   tripstrip-alert L passivetrip-crit   criticalcooling-mapsmap0 0 cpu6-thermal   tripstrip-alert L passivetrip-crit   criticalcooling-mapsmap0 0 cpu7-thermal   tripstrip-alert L passivetrip-crit   criticalcooling-mapsmap0 0 vpu0-thermal   tripstrip-alert L passivetrip-crit   criticalvpu1-thermal   tripstrip-alert L passivetrip-crit   criticalgpu-thermal   tripstrip-alert L passivetrip-crit   criticalgpu1-thermal   tripstrip-alert L passivetrip-crit   criticalvdec-thermal   tripstrip-alert L passivetrip-crit   criticalimg-thermal   tripstrip-alert L passivetrip-crit   criticalinfra-thermal   tripstrip-alert L passivetrip-crit   criticalcam0-thermal   tripstrip-alert L passivetrip-crit   criticalcam1-thermal   tripstrip-alert L passivetrip-crit   criticalchosen serial0:921600n8firmwareopteelinaro,optee-tzsmcmemory@40000000memory@reserved-memory+ioptee@43200000 C memory@50000000shared-dma-poolP .memory@53000000shared-dma-poolS@memory@54600000 T` memory@60000000shared-dma-pool` 4memory@60f00000shared-dma-pool` 6memory@61000000shared-dma-poola 3memory@62000000shared-dma-poolb@backlight-lcm0pwm-backlight  @ 5 L backlight-lcd1pwm-backlight L  B.  5 @ udisabledcan-clk fixed-clock-1-can-clk>regulator-0regulator-fixed{edp_panel_3v32Z2Z Q defaultregulator-1regulator-fixed{edp_backlight_12v Q `defaultgpio-keys gpio-keysbutton-volume-upR dd /j volume_up vsregulator-vio18-lcm0regulator-fixed {vio18_lcm0 Q /default regulator-vsys-lcm0regulator-fixed {vsys_lcm0  lregulator-2regulator-fixed {wifi_3v32Z2Z  Q compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1gce0gce1ethdr0mutex0mutex1merge1merge2merge3merge4merge5vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7serial0ethernet0device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedinterruptscpusstatusnum-channelswakeup-delay-msmediatek,platformpinctrl-namespinctrl-0audio-routingmediatek,adsplink-namesound-dai#clock-cellsclocksclock-divclock-multclock-output-names#performance-domain-cellsopp-sharedopp-hzopp-microvoltrangesdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxoutput-highdrive-strengthinput-enableinput-disablebias-disablebias-pull-updrive-strength-microampbias-pull-downoutput-low#power-domain-cellsdomain-supplyclock-namesmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parents#sound-dai-cellsinterrupts-extended#io-channel-cellsmediatek,mic-type-0mediatek,mic-type-1mediatek,mic-type-2regulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesmediatek,long-press-modepower-off-time-seclinux,keycodeswakeup-source#iommu-cells#mbox-cellsmemory-regionfirmware-namepower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-namesnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsmediatek,pad-selectcs-gpiosspi-max-frequencyvdd-supplyxceiver-supplyinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrphy-modephy-handlesnps,reset-gpiosnps,reset-delays-usmediatek,tx-delay-psmediatek,mac-wolpinctrl-1snps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,weightsnps,priorityphysmediatek,syscon-wakeupdr_modeusb-role-switchvusb33-supplyremote-endpointbus-widthcap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vcap-mmc-hw-resetno-sdiono-sdhs400-ds-delayvmmc-supplyvqmmc-supplynon-removablecap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104no-mmcfreq-table-hzmediatek,ufs-disable-mcqbus-rangeiommu-mapiommu-map-maskphy-namesinterrupt-map-maskinterrupt-mapbits#phy-cellsrichtek,vinovp-microvoltLDO_VIN3-supplylabeldata-roleop-sink-microwattpower-roletry-power-rolesource-pdossink-pdospd-revisionsvidvdoirq-gpiosreset-gpiosAVDD28-supplyvcc-supplymode-switchorientation-switchmediatek,force-modeoperating-points-v2power-domain-namesmali-supplymediatek,gce-client-regmediatek,gce-eventsmediatek,scpiommus#dma-cellsmediatek,smimediatek,larb-idmediatek,larbsbacklightenable-gpiosiovcc-supplymediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzpolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicestdout-pathno-mapbrightness-levelsdefault-brightness-levelnum-interpolated-stepspwmsenable-active-highdebounce-intervallinux,codevin-supplyregulator-boot-on