80( }$rockchip,rk3328-evbrockchip,rk3328 +7Rockchip RK3328 EVBaliases=/pinctrl/gpio@ff210000C/pinctrl/gpio@ff220000I/pinctrl/gpio@ff230000O/pinctrl/gpio@ff240000U/serial@ff110000]/serial@ff120000e/serial@ff130000m/i2c@ff150000r/i2c@ff160000w/i2c@ff170000|/i2c@ff180000/ethernet@ff550000/mmc@ff500000/mmc@ff510000/mmc@ff520000cpus+cpu@0cpuarm,cortex-a53xpsci @+8E@Wdu cpu@1cpuarm,cortex-a53xpsci @+8E@Wdu cpu@2cpuarm,cortex-a53xpsci @+8E@Wdu cpu@3cpuarm,cortex-a53xpsci @+8E@Wdu idle-statespscicpu-sleeparm,idle-statexl2-cachecache@-opp-table-0operating-points-v2 opp-408000000Q~)@:opp-600000000#F~)@opp-8160000000,B@)@opp-1008000000<)@opp-1200000000G()@opp-1296000000M?d )@analog-soundsimple-audio-cardFi2s_yAnalog disabledsimple-audio-card,cpusimple-audio-card,codecarm-pmuarm,cortex-a53-pmu0defg display-subsystemrockchip,display-subsystem hdmi-soundsimple-audio-cardFi2s_yHDMI disabledsimple-audio-card,cpusimple-audio-card,codecpsciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer0   xin24m fixed-clockn6xin24mDi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s )7i2s_clki2s_hclk  txrx disabledi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s *8i2s_clki2s_hclktxrx disabledi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s +9i2s_clki2s_hclktxrx disabledspdif@ff030000rockchip,rk3328-spdif .: mclkhclk tx!default/ disabledpdm@ff040000 rockchip,pdm=Rpdm_clkpdm_hclkrx!defaultsleep/9 disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfdBio-domains"rockchip,rk3328-io-voltage-domain disabledgpiorockchip,rk3328-grf-gpioCSpower-controller!rockchip,rk3328-power-controller_+9power-domain@1_power-domain@6D_power-domain@5 BAB_power-domain@8F_reboot-modesyscon-reboot-modeszRBRBRB RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart 7&baudclkapb_pclktxrx!default / disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart 8'baudclkapb_pclktxrx!default / ! disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart 9(baudclkapb_pclktxrx!default/"okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c $+7 i2cpclk!default/# disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c %+8 i2cpclk!default/$okaypmic@18rockchip,rk805 %xin32krk805-clkout2CS!default/&''''()(regulatorsDCDC_REG1 5vdd_logicD 4\ tregulator-state-memB@DCDC_REG25vdd_armD 4\ tregulator-state-mem~DCDC_REG35vcc_ddrtregulator-state-memDCDC_REG45vcc_ioD2Z\2Zt(regulator-state-mem2ZLDO_REG15vcc_18Dw@\w@tregulator-state-memw@LDO_REG2 5vcc18_emmcDw@\w@tregulator-state-memw@LDO_REG35vdd_10DB@\B@tregulator-state-memB@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c &+9 i2cpclk!default/) disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c '+: i2cpclk!default/* disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi 1+ spiclkapb_pclk txrx!default/+,-. disabledwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt (pwm@ff1b0000rockchip,rk3328-pwm< pwmpclk!default// disabledpwm@ff1b0010rockchip,rk3328-pwm< pwmpclk!default/0 disabledpwm@ff1b0020rockchip,rk3328-pwm < pwmpclk!default/1 disabledpwm@ff1b0030rockchip,rk3328-pwm0< pwmpclk!default/2 disableddma-controller@ff1f0000arm,pl330arm,primecell@ apb_pclkthermal-zonessoc-thermal13tripstrip-point0ApMpassivetrip-point1ALMpassive4soc-critAsM criticalcooling-mapsmap0X40] lmap1X4 ]5ltsadc@ff250000rockchip,rk3328-tsadc% :y$P$tsadcapb_pclk!initdefaultsleep/6976B tsadc-apbokay3efuse@ff260000rockchip,rk3328-efuse&P+> pclk_efuse id@7cpu-leakage@17logic-leakage@19cpu-version@1aEadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( P%saradcapb_pclkV saradc-apb disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-4500TZW]XY[\"gpgpmmupppp0ppmmu0pp1ppmmu1 buscore8#9f5opp-table-gpuoperating-points-v28opp-200000000 g8opp-300000000g8opp-400000000ׄg8opp-500000000e0 disablediommu@ff330200rockchip,iommu3 ` aclkiface1 disablediommu@ff340800rockchip,iommu4@ bF aclkiface1 disabledvideo-codec@ff350000rockchip,rk3328-vpu5  vdpuF aclkhclk>:#9iommu@ff350800rockchip,iommu5@  F aclkiface1#9:video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec6  BABaxiahbcabaccoreyAB ׄׄ>;#9iommu@ff360480rockchip,iommu 6@6@ JB aclkiface1#9;vop@ff370000rockchip,rk3328-vop7>  x;aclk_vopdclk_vophclk_vop axiahbdclk>< disabledport endpointE=Ciommu@ff373f00rockchip,iommu7?  ; aclkiface1 disabled<hdmi@ff3c0000rockchip,rk3328-dw-hdmi< #FiahbisfrcecU>Zhdmi!default /?@AdB disabledports+port@0endpointEC=port@1codec@ff410000rockchip,rk3328-codecA* pclkmclkdB disabledphy@ff430000rockchip,rk3328-hdmi-phyC SDysysclkrefoclkrefpclk hdmi_phyqE }cpu-version disabled>clock-controller@ff440000rockchip,rk3328-cruDDxin24mdByx=&'(ABDC"\5H4$zDDD|n6n6n6ׄn6#FLGрxhxhрxhxhsyscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2phy@100rockchip,rk3328-usb2phyDphyclk usb480m_phyy{FokayFotg-port$;<=otg-bvalidotg-idlinestateokayWhost-port > linestateokayXmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@   =!JNbiuciuciu-driveciu-sampleрmresetokay!default/GHIJKmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@   >"KObiuciuciu-driveciu-sampleрnresetokay'=LH!default /MNOmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@  ?#LPbiuciuciu-driveciu-sampleрoresetokayH!default /PQRethernet@ff540000rockchip,rk3328-gmacT macirq8dWXZYMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macc stmmacethdBVdr disabledethernet@ff550000rockchip,rk3328-gmacUdB macirq8TSSUVIstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphyb stmmaceth}rmiiSVdroutputokayTyeTmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22Vd!default/UVSusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X Motgotg@ UW Zusb2-phyokayusb@ff5c0000 generic-ehci\  NFUXZusbokayusb@ff5d0000 generic-ohci]  NFUXZusbokaymmc@ff5f00000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc_@  @MQbiuciuciu-driveciu-sampleрhreset disabledusb@ff600000rockchip,rk3328-dwc3snps,dwc3` C`aref_clksuspend_clkbus_clkotg utmi_wide1Ik disabledinterrupt-controller@ff811000 arm,gic-400@ @ `   crypto@ff060000rockchip,rk3328-crypto@ PQ;hclk_masterhclk_slavesclkD crypto-rstpinctrlrockchip,rk3328-pinctrldB+gpio@ff210000rockchip,gpio-bank! 3CSfgpio@ff220000rockchip,gpio-bank" 4CSegpio@ff230000rockchip,gpio-bank# 5CS%gpio@ff240000rockchip,gpio-bank$ 6CSpcfg-pull-up[pcfg-pull-downcpcfg-pull-none Ypcfg-pull-none-2ma  bpcfg-pull-up-2ma pcfg-pull-up-4ma \pcfg-pull-none-4ma  _pcfg-pull-down-4ma pcfg-pull-none-8ma  ]pcfg-pull-up-8ma ^pcfg-pull-none-12ma   `pcfg-pull-up-12ma  apcfg-output-high #pcfg-output-low /pcfg-input-high :Zpcfg-input :i2c0i2c0-xfer GYY#i2c1i2c1-xfer GYY$i2c2i2c2-xfer G YY)i2c3i2c3-xfer GYY*i2c3-pins GYYhdmi_i2chdmii2c-xfer GYY@pdm-0pdmm0-clk GYpdmm0-fsync GYpdmm0-sdi0 GYpdmm0-sdi1 GYpdmm0-sdi2 GYpdmm0-sdi3 GYpdmm0-clk-sleep GZpdmm0-sdi0-sleep GZpdmm0-sdi1-sleep GZpdmm0-sdi2-sleep GZpdmm0-sdi3-sleep GZpdmm0-fsync-sleep GZtsadcotp-pin G Y6otp-out G Y7uart0uart0-xfer G Y[uart0-cts G Yuart0-rts G Yuart0-rts-pin G Yuart1uart1-xfer GY[uart1-cts GY uart1-rts GY!uart1-rts-pin GYuart2-0uart2m0-xfer GY[uart2-1uart2m1-xfer GY["spi0-0spi0m0-clk G[spi0m0-cs0 G [spi0m0-tx G [spi0m0-rx G [spi0m0-cs1 G [spi0-1spi0m1-clk G[spi0m1-cs0 G[spi0m1-tx G[spi0m1-rx G[spi0m1-cs1 G[spi0-2spi0m2-clk G[+spi0m2-cs0 G[.spi0m2-tx G[,spi0m2-rx G[-i2s1i2s1-mclk GYi2s1-sclk GYi2s1-lrckrx GYi2s1-lrcktx GYi2s1-sdi GYi2s1-sdo GYi2s1-sdio1 GYi2s1-sdio2 GYi2s1-sdio3 GYi2s1-sleep GZZZZZZZZZi2s2-0i2s2m0-mclk GYi2s2m0-sclk GYi2s2m0-lrckrx GYi2s2m0-lrcktx GYi2s2m0-sdi GYi2s2m0-sdo GYi2s2m0-sleep` GZZZZZZi2s2-1i2s2m1-mclk GYi2s2m1-sclk GYi2sm1-lrckrx GYi2s2m1-lrcktx GYi2s2m1-sdi GYi2s2m1-sdo GYi2s2m1-sleepP GZZZZZspdif-0spdifm0-tx GYspdif-1spdifm1-tx GYspdif-2spdifm2-tx GYsdmmc0-0sdmmc0m0-pwren G\sdmmc0m0-pin G\sdmmc0-1sdmmc0m1-pwren G\sdmmc0m1-pin G\gsdmmc0sdmmc0-clk G]Gsdmmc0-cmd G^Hsdmmc0-dectn G\Isdmmc0-wrprt G\sdmmc0-bus1 G^sdmmc0-bus4@ G^^^^Jsdmmc0-pins G\\\\\\\\sdmmc0extsdmmc0ext-clk G_sdmmc0ext-cmd G\sdmmc0ext-wrprt G\sdmmc0ext-dectn G\sdmmc0ext-bus1 G\sdmmc0ext-bus4@ G\\\\sdmmc0ext-pins G\\\\\\\\sdmmc1sdmmc1-clk G ]Osdmmc1-cmd G ^Nsdmmc1-pwren G^sdmmc1-wrprt G^sdmmc1-dectn G^sdmmc1-bus1 G^sdmmc1-bus4@ G^^^^Msdmmc1-pins G \ \\\\\\\\emmcemmc-clk G`Pemmc-cmd GaQemmc-pwren GYemmc-rstnout GYemmc-bus1 Gaemmc-bus4@ Gaaaaemmc-bus8 GaaaaaaaaRpwm0pwm0-pin GY/pwm1pwm1-pin GY0pwm2pwm2-pin GY1pwmirpwmir-pin GY2gmac-1rgmiim1-pins` G ] __]___ _ _] ]__]]] ]_]]]]rmiim1-pins Gb`bbbb b b` ` Y YYYYYgmac2phyfephyled-speed10 GYfephyled-duplex GYfephyled-rxm1 GYUfephyled-txm1 GYfephyled-linkm1 GYVtsadc_pintsadc-int G Ytsadc-pin G Yhdmi_pinhdmi-cec GY?hdmi-hpd GcAcif-0dvp-d2d9-m0 GYYYYY Y Y YYYYYcif-1dvp-d2d9-m1 GYYYYYYYYYYYYpmicpmic-int-l G[&sdio-pwrseqwifi-enable-h GYdchosen Userial2:1500000n8regulator-dc-12vregulator-fixed5dc_12vtD\hsdio-pwrseqmmc-pwrseq-simple!default/d aeLregulator-sdmmcregulator-fixed mf!default/g5vcc_sdD2Z\2Z r(Kregulator-vcc-sysregulator-fixed5vcc_systDLK@\LK@ rh'regulator-vcc-phyregulator-fixed5vcc_phytT compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3serial0serial1serial2i2c0i2c1i2c2i2c3ethernet0mmc0mmc1mmc2device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1gpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftsystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,efuse-sizebits#io-channel-cellsinterrupt-namespower-domains#iommu-cellsiommusremote-endpointphysphy-namesrockchip,grfnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removabletx-fifo-depthrx-fifo-depthsnps,txpblphy-modephy-handleclock_in_outphy-supplyassigned-clock-ratephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathreset-gpiosgpiovin-supply