s 8lp(l8radxa,rock-2frockchip,rk3528 +7Radxa ROCK 2Faliases=/pinctrl/gpio@ff610000C/pinctrl/gpio@ffaf0000I/pinctrl/gpio@ffb00000O/pinctrl/gpio@ffb10000U/pinctrl/gpio@ffb20000[/soc/i2c@ffa58000`/soc/mmc@ffbf0000e/soc/mmc@ffc30000j/soc/serial@ff9f0000cpus+cpu-mapcluster0core0rcore1rcore2rcore3rcpu@0arm,cortex-a53vzcpupscicpu@1arm,cortex-a53vzcpupscicpu@2arm,cortex-a53vzcpupscicpu@3arm,cortex-a53vzcpupscifirmwarescmi arm,scmi-smc‚ +protocol@14vopp-table-cpuoperating-points-v2opp-1200000000G Y Y@opp-1416000000Tfr HH@opp-1608000000_" @opp-1800000000kI ԼԼ@opp-2016000000x) @opp-table-gpuoperating-points-v2-opp-300000000 Y YB@opp-500000000e Y YB@opp-600000000#F Y YB@opp-700000000)' B@opp-800000000/ ~~B@pinctrlrockchip,rk3528-pinctrl +* gpio@ff610000rockchip,gpio-bankva r s 1G<LX dyZgpio@ffaf0000rockchip,gpio-bankv  1I<LX dy Vgpio@ffb00000rockchip,gpio-bankv $ % 1K<LX @ dy gpio@ffb10000rockchip,gpio-bankv  1L<LX ` dy gpio@ffb20000rockchip,gpio-bankv  1N<LX dy Xpcfg-pull-uppcfg-pull-downpcfg-pull-nonepcfg-pull-none-drv-level-0pcfg-pull-none-drv-level-2pcfg-pull-up-drv-level-2pcfg-pull-none-smtarmclkemmcemmc-bus8Demmc-clkEemmc-cmdFemmc-strbGethfephyfephym0-led-link>fephym0-led-spd?fspigpuhdmihsmi2c0i2c1i2c1m0-xfer 1i2c2i2c2m1-xfer 3i2c3i2c4i2c4-xfer 4i2c5i2c6i2c7i2c7-xfer 5i2s0i2s1jtagpciepdmpmupwm0pwm1pwm1m0-pins6pwm2pwm2m0-pins7pwm3pwm4pwm5pwm6pwm7pwrrefrgmiiscrsdio0sdio0-bus4@Hsdio0-clkIsdio0-cmdJsdio1sdio1-bus4@ Ksdio1-clkLsdio1-cmdMsdmmcsdmmc-bus4@Nsdmmc-clkOsdmmc-cmdPsdmmc-detQsdmmc-vol-ctrl-h\spdifspi0spi1tsi0tsi1uart0uart0m0-xfer 0uart1uart2uart3uart4uart5uart6uart7bluetoothbt-wake-host-hhost-wake-bt-hledsstate-led-bUusbusb-host-en[wifiusb-wifi-pwrYwifi-reg-on-h_wifi-wake-host-hpsciarm,psci-1.0arm,psci-0.2smcreserved-memory+*shmem@10f000arm,scmi-shmemv timerarm,armv8-timer01   clock-xin24m fixed-clockn6 xin24mclock-gmac50m fixed-clock gmac0soc simple-bus*+interrupt-controller@fed01000 arm,gic-400@v @ `  1 dyqos@ff200000rockchip,rk3528-qossysconv qos@ff200080rockchip,rk3528-qossysconv qos@ff200100rockchip,rk3528-qossysconv  qos@ff200200rockchip,rk3528-qossysconv  qos@ff200280rockchip,rk3528-qossysconv  qos@ff200300rockchip,rk3528-qossysconv  qos@ff200380rockchip,rk3528-qossysconv  qos@ff210000rockchip,rk3528-qossysconv! qos@ff210080rockchip,rk3528-qossysconv! qos@ff220000rockchip,rk3528-qossysconv" qos@ff220080rockchip,rk3528-qossysconv" qos@ff240000rockchip,rk3528-qossysconv$ qos@ff250000rockchip,rk3528-qossysconv% qos@ff260000rockchip,rk3528-qossysconv& qos@ff270000rockchip,rk3528-qossysconv' qos@ff270080rockchip,rk3528-qossysconv' qos@ff270100rockchip,rk3528-qossysconv' qos@ff270200rockchip,rk3528-qossysconv' qos@ff270280rockchip,rk3528-qossysconv' qos@ff270300rockchip,rk3528-qossysconv'  qos@ff270380rockchip,rk3528-qossysconv' !qos@ff270480rockchip,rk3528-qossysconv' "qos@ff270500rockchip,rk3528-qossysconv' #qos@ff280000rockchip,rk3528-qossysconv( $qos@ff280080rockchip,rk3528-qossysconv( %qos@ff280100rockchip,rk3528-qossysconv( &qos@ff280180rockchip,rk3528-qossysconv( 'qos@ff280200rockchip,rk3528-qossysconv( (qos@ff280280rockchip,rk3528-qossysconv( )qos@ff280300rockchip,rk3528-qossysconv( *qos@ff280380rockchip,rk3528-qossysconv( +qos@ff280400rockchip,rk3528-qossysconv( ,syscon@ff340000rockchip,rk3528-vpu-grfsysconv4@syscon@ff348000$rockchip,rk3528-pipe-phy-grfsysconv4Ssyscon@ff360000rockchip,rk3528-vo-grfsysconv6:clock-controller@ff4a0000rockchip,rk3528-cruvJ t          z y  LL-Fq;;]Q沀eр Cׄ#FsY@e Bxin24mgmac0N syscon@ff540000rockchip,rk3528-ioc-grfsysconvT power-management@ff600000&rockchip,rk3528-pmusysconsimple-mfdv` power-controller!rockchip,rk3528-power-controller[+ power-domain@4v o[power-domain@5vo[ vdisabledpower-domain@6vo[power-domain@7v$o !"#[power-domain@8v$o$%&'()*+,[gpu@ff700000"rockchip,rk3528-maliarm,mali-450vp -@  BbuscoreT1XYV\]Z["}gpgpmmupppp0ppmmu0pp1ppmmu1-  wvokay.spi@ff9c0000(rockchip,rk3528-spirockchip,rk3066-spiv Bspiclkapb_pclk 1//txrx + vdisabledspi@ff9d0000(rockchip,rk3528-spirockchip,rk3066-spiv Bspiclkapb_pclk 1//txrx + vdisabledserial@ff9f0000&rockchip,rk3528-uartsnps,dw-apb-uartv  kBbaudclkapb_pclk 1(/ /vokaydefault0serial@ff9f8000&rockchip,rk3528-uartsnps,dw-apb-uartv  Bbaudclkapb_pclk 1)/ /   vdisabledserial@ffa00000&rockchip,rk3528-uartsnps,dw-apb-uartv  Bbaudclkapb_pclk 1*/ /   vdisabledserial@ffa08000&rockchip,rk3528-uartsnps,dw-apb-uartv  Bbaudclkapb_pclk 1+//  vdisabledserial@ffa10000&rockchip,rk3528-uartsnps,dw-apb-uartv  1Bbaudclkapb_pclk 1,//  vdisabledserial@ffa18000&rockchip,rk3528-uartsnps,dw-apb-uartv " Bbaudclkapb_pclk 1-//  vdisabledserial@ffa20000&rockchip,rk3528-uartsnps,dw-apb-uartv % Bbaudclkapb_pclk 1.//  vdisabledserial@ffa28000&rockchip,rk3528-uartsnps,dw-apb-uartv ( Bbaudclkapb_pclk 1///  vdisabledi2c@ffa50000(rockchip,rk3528-i2crockchip,rk3399-i2cv  Bi2cpclk 1= + vdisabledi2c@ffa58000(rockchip,rk3528-i2crockchip,rk3399-i2cv  Bi2cpclk 1> +vokaydefault1eeprom@50belling,bl24c16aatmel,24c16vP2i2c@ffa60000(rockchip,rk3528-i2crockchip,rk3399-i2cv j i Bi2cpclk 1?default3+ vdisabledi2c@ffa68000(rockchip,rk3528-i2crockchip,rk3399-i2cv  Bi2cpclk 1@ + vdisabledi2c@ffa70000(rockchip,rk3528-i2crockchip,rk3399-i2cv 3 2 Bi2cpclk 1Adefault4 + vdisabledi2c@ffa78000(rockchip,rk3528-i2crockchip,rk3399-i2cv  Bi2cpclk 1B + vdisabledi2c@ffa80000(rockchip,rk3528-i2crockchip,rk3399-i2cv  Bi2cpclk 1C + vdisabledi2c@ffa88000(rockchip,rk3528-i2crockchip,rk3399-i2cv 5 4 Bi2cpclk 1Ddefault5 + vdisabledpwm@ffa90000(rockchip,rk3528-pwmrockchip,rk3328-pwmv o n Bpwmpclk vdisabledpwm@ffa90010(rockchip,rk3528-pwmrockchip,rk3328-pwmv o n Bpwmpclkvokaydefault6]pwm@ffa90020(rockchip,rk3528-pwmrockchip,rk3328-pwmv  o n Bpwmpclkvokaydefault7^pwm@ffa90030(rockchip,rk3528-pwmrockchip,rk3328-pwmv0 o n Bpwmpclk vdisabledpwm@ffa98000(rockchip,rk3528-pwmrockchip,rk3328-pwmv r q Bpwmpclk vdisabledpwm@ffa98010(rockchip,rk3528-pwmrockchip,rk3328-pwmv r q Bpwmpclk vdisabledpwm@ffa98020(rockchip,rk3528-pwmrockchip,rk3328-pwmv  r q Bpwmpclk vdisabledpwm@ffa98030(rockchip,rk3528-pwmrockchip,rk3328-pwmv0 r q Bpwmpclk vdisabledadc@ffae0000rockchip,rk3528-saradcv Bsaradcapb_pclk 1  o saradc-apbvokay%8Tethernet@ffbd0000&rockchip,rk3528-gmacsnps,dwmac-4.20av0      >Bstmmacethclk_mac_refmac_clk_rxmac_clk_txpclk_macaclk_mac1qt}macirqeth_wake_irq19? 9stmmac-axi-config;rx-queues-config<queue0tx-queues-config=queue0ethernet@ffbe0000&rockchip,rk3528-gmacsnps,dwmac-4.20av (Bstmmacethclk_mac_refpclk_macaclk_mac1y|}macirqeth_wake_irq  a stmmaceth@EAUfByC vdisabledmdiosnps,dwmac-mdio+stmmac-axi-configArx-queues-configBqueue0tx-queues-configCqueue0mmc@ffbf00000rockchip,rk3528-dwcmshcrockchip,rk3588-dwcmshcv  - n6 ( Bcorebusaxiblocktimer 1 defaultDEFG ( A B C D Ecorebusaxiblocktimervokay '6<DR2^8mmc@ffc100000rockchip,rk3528-dw-mshcrockchip,rk3288-dw-mshcv@  Bbiuciuciu-driveciu-samplek 1 default HIJ  greset vdisabledmmc@ffc200000rockchip,rk3528-dw-mshcrockchip,rk3288-dw-mshcv@  Bbiuciuciu-driveciu-samplek 1 default KLM  hreset vdisabledmmc@ffc300000rockchip,rk3528-dw-mshcrockchip,rk3288-dw-mshcv@ ( '  Bbiuciuciu-driveciu-samplek 1defaultNOPQ  resetvZvokay R2^Rdma-controller@ffd60000arm,pl330arm,primecellv@ ^ Bapb_pclkl1/phy@ffdc0000rockchip,rk3528-naneng-combphyv {- {  Brefapbpipe  c ephyapb@S vdisabledchosenserial0:1500000n8adc-keys adc-keysT+buttons<w@Vdbutton-maskromdMASKROMjuleds gpio-ledsdefaultUled-0on heartbeat V heartbeatregulator-0v9-vddregulator-fixedvdd_0v9  -Wregulator-1v1-vcc-ddrregulator-fixedvcc_ddr-Wregulator-1v8-vccregulator-fixedvcc_1v8w@w@-28regulator-3v3-vccregulator-fixedvcc_3v32Z2Z-W2regulator-3v3-vcc-wifiregulator-fixed8 XdefaultY vcc_wifi2Z2Z-2regulator-5v0-vcc-sysregulator-fixed vcc5v0_sysLK@LK@Wregulator-5v0-vcc-usb20regulator-fixed8 Zdefault[ vcc5v0_usb20LK@LK@-Wregulator-vccio-sdregulator-gpio Vdefault\ vccio_sdw@2ZKw@2Z-WRregulator-vdd-armpwm-regulatorR]WWvdd_arm bShbregulator-vdd-logicpwm-regulatorR^WW vdd_logic Yb.rfkill rfkill-gpio drfkill-wlandefault_wlan V compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c1mmc0mmc1serial0cpuregdevice_typeenable-methodclocksoperating-points-v2cpu-supplyphandlearm,smc-idshmem#clock-cellsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrockchip,grfrangesinterruptsgpio-controller#gpio-cellsgpio-rangesinterrupt-controller#interrupt-cellspower-domainsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsno-mapclock-frequencyclock-output-namesassigned-clocksassigned-clock-ratesclock-names#reset-cells#power-domain-cellspm_qosstatusinterrupt-namesresetsmali-supplydmasdma-namesreg-io-widthreg-shiftpinctrl-namespinctrl-0pagesizeread-onlyvcc-supply#pwm-cellsreset-names#io-channel-cellsvref-supplyphy-handlephy-modesnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsophy-is-integratedsnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usemax-frequencybus-widthcap-mmc-highspeedmmc-hs200-1_8vno-sdno-sdionon-removablevmmc-supplyvqmmc-supplyfifo-depthrockchip,default-sample-phasecap-sd-highspeeddisable-wpsd-uhs-sdr104#dma-cellsarm,pl330-periph-burst#phy-cellsrockchip,pipe-grfrockchip,pipe-phy-grfstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltcolordefault-statefunctiongpioslinux,default-triggerregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltvin-supplyenable-active-highstatespwmspwm-supplyregulator-settling-time-up-usradio-typeshutdown-gpios