8( .p&firefly,roc-rk3328-pcrockchip,rk3328 +7Firefly ROC-RK3328-PCaliases=/pinctrl/gpio@ff210000C/pinctrl/gpio@ff220000I/pinctrl/gpio@ff230000O/pinctrl/gpio@ff240000U/serial@ff110000]/serial@ff120000e/serial@ff130000m/i2c@ff150000r/i2c@ff160000w/i2c@ff170000|/i2c@ff180000/ethernet@ff540000/mmc@ff500000/mmc@ff520000cpus+cpu@0cpuarm,cortex-a53xpsci@&3@@R_p{ cpu@1cpuarm,cortex-a53xpsci@&3@@R_p{ cpu@2cpuarm,cortex-a53xpsci@&3@@R_p{ cpu@3cpuarm,cortex-a53xpsci@&3@@R_p{ idle-statespscicpu-sleeparm,idle-statex{l2-cachecache @({opp-table-0operating-points-v2{opp-408000000Q~$@5opp-600000000#F~$@opp-8160000000,B@$@opp-1008000000<$@opp-1200000000G($@opp-1296000000M?d $@analog-soundsimple-audio-cardAi2sZtAnalogokaysimple-audio-card,cpusimple-audio-card,codecarm-pmuarm,cortex-a53-pmu0defg display-subsystemrockchip,display-subsystem hdmi-soundsimple-audio-cardAi2sZtHDMIokaysimple-audio-card,cpusimple-audio-card,codecpsciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer0   xin24m fixed-clockn6xin24m{Ii2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s )7i2s_clki2s_hclk  txrx okay{i2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s *8i2s_clki2s_hclktxrx okay{i2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s +9i2s_clki2s_hclktxrx  disabledspdif@ff030000rockchip,rk3328-spdif .: mclkhclk txdefault*  disabledpdm@ff040000 rockchip,pdm=Rpdm_clkpdm_hclkrxdefaultsleep*4 disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd{Fio-domains"rockchip,rk3328-io-voltage-domainokay>LZhvgpiorockchip,rk3328-grf-gpio{Hpower-controller!rockchip,rk3328-power-controller+{<power-domain@1power-domain@6Dpower-domain@5 BABpower-domain@8Freboot-modesyscon-reboot-modeRBRBRB RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart 7&baudclkapb_pclktxrxdefault * !"  disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart 8'baudclkapb_pclktxrxdefault *#$%  disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart 9(baudclkapb_pclktxrxdefault*& okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c $+7 i2cpclkdefault*' disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c %+8 i2cpclkdefault*(okaypmic@18rockchip,rk805xin32krk805-clkout2default*)#;I*U*a*m*y +{nregulatorsDCDC_REG1 vdd_logic 4 {=regulator-state-memB@DCDC_REG2vdd_arm 4 {regulator-state-mem~DCDC_REG3vcc_ddrregulator-state-memDCDC_REG4vcc_io2Z2Z{regulator-state-mem2ZLDO_REG1vcc_18w@w@{regulator-state-memw@LDO_REG2 vcc18_emmcw@w@{regulator-state-memw@LDO_REG3vdd_10B@B@regulator-state-memB@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c &+9 i2cpclkdefault*, disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c '+: i2cpclkdefault*- disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi 1+ spiclkapb_pclk txrxdefault*./01 disabledwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt (pwm@ff1b0000rockchip,rk3328-pwm< pwmpclkdefault*2* disabledpwm@ff1b0010rockchip,rk3328-pwm< pwmpclkdefault*3* disabledpwm@ff1b0020rockchip,rk3328-pwm < pwmpclkdefault*4* disabledpwm@ff1b0030rockchip,rk3328-pwm0< pwmpclkdefault*5* disableddma-controller@ff1f0000arm,pl330arm,primecell@5 apb_pclkL{thermal-zonessoc-thermalWm{6tripstrip-point0ppassivetrip-point1Lpassive{7soc-crits criticalcooling-mapsmap070 map17 8tsadc@ff250000rockchip,rk3328-tsadc% :$P$tsadcapb_pclkinitdefaultsleep*94:9B  tsadc-apb.okay{6efuse@ff260000rockchip,rk3328-efuse&P+> pclk_efuseD id@7cpu-leakage@17logic-leakage@19cpu-version@1aX{Jadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( P]%saradcapb_pclkV  saradc-apbokayo{ogpu@ff300000"rockchip,rk3328-maliarm,mali-4500TZW]XY[\"{gpgpmmupppp0ppmmu0pp1ppmmu1 buscore;<f={8opp-table-gpuoperating-points-v2{;opp-200000000 g8opp-300000000g8opp-400000000ׄg8opp-500000000e0 disablediommu@ff330200rockchip,iommu3 ` aclkiface disablediommu@ff340800rockchip,iommu4@ bF aclkiface disabledvideo-codec@ff350000rockchip,rk3328-vpu5  {vdpuF aclkhclk><iommu@ff350800rockchip,iommu5@  F aclkiface<{>video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec6  BABaxiahbcabaccoreAB ׄׄ?<iommu@ff360480rockchip,iommu 6@6@ JB aclkiface<{?vop@ff370000rockchip,rk3328-vop7>  x;aclk_vopdclk_vophclk_vop  axiahbdclk@okayport{ endpointA{Giommu@ff373f00rockchip,iommu7?  ; aclkifaceokay{@hdmi@ff3c0000rockchip,rk3328-dw-hdmi<  #FiahbisfrcecBhdmidefault *CDEF okay{ports+port@0endpointG{Aport@1codec@ff410000rockchip,rk3328-codecA* pclkmclkF okay H{phy@ff430000rockchip,rk3328-hdmi-phyC SIysysclkrefoclkrefpclk hdmi_phyJ cpu-version okay{Bclock-controller@ff440000rockchip,rk3328-cruDIxin24mFx=&'(ABDC"\5H4$%zIII|n6n6n6ׄn6#FLGрxhxhрxhxh{syscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2phy@100rockchip,rk3328-usb2phyIphyclk usb480m_phy{%Kokay{Kotg-port $;<={otg-bvalidotg-idlinestateokay{[host-port  > {linestateokay{\mmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@   =!JNbiuciuciu-driveciu-sample<Gрm resetokayU_qdefault*LMNOPmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@   >"KObiuciuciu-driveciu-sample<Gрn reset disabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@  ?#LPbiuciuciu-driveciu-sample<Gрo resetokayU_default *QRSethernet@ff540000rockchip,rk3328-gmacT {macirq8dWXZYMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macc  stmmacethF!okaydf%TT,input9UDrgmiidefault*VM VWf |'P$ethernet@ff550000rockchip,rk3328-gmacUF {macirq8TSSUVIstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphyb  stmmacethDrmiiX!,output disabledmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22Vddefault*YZ{Xusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X Motghost@ [ usb2-phyokayusb@ff5c0000 generic-ehci\  NK\usbokayusb@ff5d0000 generic-ohci]  NK\usbokaymmc@ff5f00000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc_@  @MQbiuciuciu-driveciu-sample<Gрh reset disabledusb@ff600000rockchip,rk3328-dwc3snps,dwc3` C`aref_clksuspend_clkbus_clkhost utmi_wide  - E g  okayinterrupt-controller@ff811000 arm,gic-400  @ @ `   {crypto@ff060000rockchip,rk3328-crypto@ PQ;hclk_masterhclk_slavesclkD  crypto-rstpinctrlrockchip,rk3328-pinctrlF+ gpio@ff210000rockchip,gpio-bank! 3  {+gpio@ff220000rockchip,gpio-bank" 4  {Wgpio@ff230000rockchip,gpio-bank# 5  {lgpio@ff240000rockchip,gpio-bank$ 6  {rpcfg-pull-up {_pcfg-pull-down {gpcfg-pull-none {]pcfg-pull-none-2ma  {fpcfg-pull-up-2ma  pcfg-pull-up-4ma  {`pcfg-pull-none-4ma  {cpcfg-pull-down-4ma  pcfg-pull-none-8ma  {apcfg-pull-up-8ma  {bpcfg-pull-none-12ma   {dpcfg-pull-up-12ma   {epcfg-output-high pcfg-output-low +pcfg-input-high  6{^pcfg-input 6i2c0i2c0-xfer C]]{'i2c1i2c1-xfer C]]{(i2c2i2c2-xfer C ]]{,i2c3i2c3-xfer C]]{-i2c3-pins C]]hdmi_i2chdmii2c-xfer C]]{Dpdm-0pdmm0-clk C]{pdmm0-fsync C]pdmm0-sdi0 C]{pdmm0-sdi1 C]{pdmm0-sdi2 C]{pdmm0-sdi3 C]{pdmm0-clk-sleep C^{pdmm0-sdi0-sleep C^{pdmm0-sdi1-sleep C^{pdmm0-sdi2-sleep C^{pdmm0-sdi3-sleep C^{pdmm0-fsync-sleep C^tsadcotp-pin C ]{9otp-out C ]{:uart0uart0-xfer C ]_{ uart0-cts C ]{!uart0-rts C ]{"uart0-rts-pin C ]uart1uart1-xfer C]_{#uart1-cts C]{$uart1-rts C]{%uart1-rts-pin C]uart2-0uart2m0-xfer C]_uart2-1uart2m1-xfer C]_{&spi0-0spi0m0-clk C_spi0m0-cs0 C _spi0m0-tx C _spi0m0-rx C _spi0m0-cs1 C _spi0-1spi0m1-clk C_spi0m1-cs0 C_spi0m1-tx C_spi0m1-rx C_spi0m1-cs1 C_spi0-2spi0m2-clk C_{.spi0m2-cs0 C_{1spi0m2-tx C_{/spi0m2-rx C_{0i2s1i2s1-mclk C]i2s1-sclk C]i2s1-lrckrx C]i2s1-lrcktx C]i2s1-sdi C]i2s1-sdo C]i2s1-sdio1 C]i2s1-sdio2 C]i2s1-sdio3 C]i2s1-sleep C^^^^^^^^^i2s2-0i2s2m0-mclk C]i2s2m0-sclk C]i2s2m0-lrckrx C]i2s2m0-lrcktx C]i2s2m0-sdi C]i2s2m0-sdo C]i2s2m0-sleep` C^^^^^^i2s2-1i2s2m1-mclk C]i2s2m1-sclk C]i2sm1-lrckrx C]i2s2m1-lrcktx C]i2s2m1-sdi C]i2s2m1-sdo C]i2s2m1-sleepP C^^^^^spdif-0spdifm0-tx C]spdif-1spdifm1-tx C]spdif-2spdifm2-tx C]{sdmmc0-0sdmmc0m0-pwren C`sdmmc0m0-pin C`sdmmc0-1sdmmc0m1-pwren C`sdmmc0m1-pin C`{hsdmmc0sdmmc0-clk Ca{Lsdmmc0-cmd Cb{Msdmmc0-dectn C`{Nsdmmc0-wrprt C`sdmmc0-bus1 Cbsdmmc0-bus4@ Cbbbb{Osdmmc0-pins C````````sdmmc0extsdmmc0ext-clk Ccsdmmc0ext-cmd C`sdmmc0ext-wrprt C`sdmmc0ext-dectn C`sdmmc0ext-bus1 C`sdmmc0ext-bus4@ C````sdmmc0ext-pins C````````sdmmc1sdmmc1-clk C asdmmc1-cmd C bsdmmc1-pwren Cbsdmmc1-wrprt Cbsdmmc1-dectn Cbsdmmc1-bus1 Cbsdmmc1-bus4@ Cbbbbsdmmc1-pins C ` ````````emmcemmc-clk Cd{Qemmc-cmd Ce{Remmc-pwren C]emmc-rstnout C]emmc-bus1 Ceemmc-bus4@ Ceeeeemmc-bus8 Ceeeeeeee{Spwm0pwm0-pin C]{2pwm1pwm1-pin C]{3pwm2pwm2-pin C]{4pwmirpwmir-pin C]{5gmac-1rgmiim1-pins` C a ccaccc c ca accaaa acaaaa{Vrmiim1-pins Cfdffff f fd d ] ]]]]]gmac2phyfephyled-speed10 C]fephyled-duplex C]fephyled-rxm1 C]{Yfephyled-txm1 C]fephyled-linkm1 C]{Ztsadc_pintsadc-int C ]tsadc-pin C ]hdmi_pinhdmi-cec C]{Chdmi-hpd Cg{Ecif-0dvp-d2d9-m0 C]]]]] ] ] ]]]]]cif-1dvp-d2d9-m1 C]]]]]]]]]]]]irir-int C]{mpmicpmic-int-l C_{)usb2usb20-host-drv C_{jsdmmciosdio-per-pin Cg{iwifiwifi-en C]{pwifi-host-wake Cc{qbt-rst C]bt-en C]chosen Qserial2:1500000n8external-gmac-clock fixed-clocksY@ gmac_clkin{Tregulator-dc-12vregulator-fixeddc_12v{kregulator-sdmmcregulator-fixed a+default*hvcc_sd2Z2Z ]{Pregulator-sdmmcioregulator-gpiow@2Z vcc_sdio hvoltagew@2Z ]* +default*i{regulator-vcc-host1-5vregulator-fixed wdefault*j vcc_host1_5v ]* a+regulator-vcc-sysregulator-fixedvcc_sysLK@LK@ ]k{*regulator-vcc-phyregulator-fixedvcc_phy{Uir-receivergpio-ir-receiver l*mdefault rc-khadasleds gpio-ledsled-0 firefly:blue:power heartbeat n onled-1 firefly:yellow:user mmc1 n offadc-keys adc-keys o buttons button-recovery Recovery h 'sdio-pwrseqmmc-pwrseq-simpledefault*pq "r compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3serial0serial1serial2i2c0i2c1i2c2i2c3ethernet0mmc0mmc1device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1vccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplypmuio-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftsystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,efuse-sizebits#io-channel-cellsvref-supplyinterrupt-namespower-domainsmali-supply#iommu-cellsiommusremote-endpointphysphy-namesrockchip,grfmute-gpiosnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymmc-ddr-1_8vmmc-hs200-1_8vnon-removabletx-fifo-depthrx-fifo-depthsnps,txpblclock_in_outphy-supplyphy-modesnps,aalsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ussnps,rxpbltx_delayrx_delayphy-handlephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathvin-supplyregulator-typeenable-active-highlinux,rc-map-namelabellinux,default-triggerdefault-stateio-channelsio-channel-nameskeyup-threshold-microvoltlinux,codepress-threshold-microvoltreset-gpios