detailed TODO list for Qucs and status by priority

- Verilog schematic support
 - Eqn
 - Diagrams
- device library file format
 - Upgrade format
 - add electrical models
- Update Component edit dialog
 - label, attributes, parameters
- Support connectivity not related to geometry, "rat nets"
 - refactor nodemap
 - GUI support for invisible/implicit connections
- Verilog style circuit design
  - parameters in schematics
  - wire types, disciplines, mixed signal modelling
  - buses
- rework "simulate" button
  - bypass "netlisting" if unnecessary
  - rely on external tool
  - drop netlisting code
