Route two matched capacitors, C1 and C2, drawn in a capacitor matrix. More...

Public Member Functions | |
| __init__ (self, capacitorInstance, capacitor, minimizeVRT=False) | |
| This is the class constructor. | |
| __setStretching__ (self) | |
| Sets vertical stretching value considering spacing between elementary capacitors in the matrix. | |
| setRules (self) | |
| Defines technology rules used to draw the layout. | |
| create (self) | |
| Draw the compact or matrix of capacitors. | |
| drawVRoutingTracks (self, vRoutingTracksLayer) | |
Iteratively draws vertical routing tracks given the physical layer vRoutingTracksLayer. | |
Public Member Functions inherited from CapacitorStack | |
| __isUnitCap__ (self) | |
| __isMatchingSchemeOK__ (self) | |
| capacitorIdOccurence (self, capacitorIdentifier) | |
| capacitorLine (self, dy, abutmentBox_spacing, matchingSchemeRowIndex=0) | |
Iteratively draws a horizontal or vertical line of capacitors according to the direction parameter. | |
| capacitorMatrix (self, abutmentBox_spacing=0) | |
| Draws a matrix of identical capacitors. | |
| drawAbutmentBox (self, abutmentBox_spacing=0) | |
| Draws the abutment box of the matrix or campact capacitor. | |
| drawBottomPlatesRLayers (self, bottomPlateRLayer, drawnCapacitor) | |
| Draws the routing layers connecting the bottom plate in the matrix of capacitors. | |
| drawTopPlatesRLayers (self, topPlateRLayer, drawnCapacitor) | |
| Draws the routing layers connecting the top plates in the matrix of capacitors. | |
| getVerticalRoutingTrack_width (self) | |
| getMatrixDim (self) | |
| getMatchingScheme (self) | |
Public Member Functions inherited from CapacitorUnit | |
| __setCapacitorPerUnit__ (self, capacitorType) | |
Sets the area and perimeter capacitances as specified in 350 nm AMS technology and according to capacitorType (MIM or PIP). | |
| __computeCapDim__ (self, capacitance, capacitorType) | |
| Computes width and length of the capacitor. | |
| __isCapacitorUnitOK__ (self, capDim) | |
| Checks if the computed capacitor dimensions exceed or are less than maximum and minimum limits, respectively, as specified in technology rules. | |
| getCapacitorType (self) | |
| getMaximumCapWidth (self) | |
| getMinimumCapWidth (self) | |
| getLayers (self) | |
| Loads the technology file then extracts the adequate layers according to the capacitor type (MIM or PIP). | |
| drawCapacitor (self, layerDict, t, b) | |
| Draws all layout physicial layers of the capacitor. | |
| computeBottomPlateCuts (self) | |
| Computes needed parameters to draw bottom plate cuts in its exact position, including : | |
| computeTopPlateCuts (self) | |
| Computes needed parameters to draw top plate cuts in its exact position, including : | |
| drawOnePlate (self, layer, net, boxDimensions) | |
| Draws the top or bottom plate through inflation of the Box under it. | |
| drawBottomPlateCut (self, layer, b) | |
| Draws the required cuts to connect the bottom plate. | |
| drawTopPlateCut (self, layer, t) | |
| Draws the top plate's cuts after computing the maximal number of cuts that can be placed and its exact enclosure in the top plate. | |
| drawRoutingLayers (self, bottomPlateLayer, topPlateLayer, t, b) | |
| Draws the routing layers of both bottom and top plates after computing widths and the exact position of these layers. | |
| cutMaxNumber (self, width_layer, width_cut, spacing_cut, enclosure_cut) | |
Computes the maximal number of cuts to be placed on a layer of width width_layer considering specifications such as the spacing between the cuts, its width and its enclosure in the layer. | |
| cutLine (self, net, layer, firstCutXCenter, firstCutYCenter, width_cut, height_cut, spacing_cut, cutNumber, direction) | |
| Creates a horizontal or vertical line of contacts according to the specified direction. | |
| cutMatrix (self, net, layer, firstCutXCenter, firstCutYCenter, width_cut, height_cut, spacing_cut, cutColumnNumber, cutRowNumber) | |
| Creates a matrix of cuts by vertically stacking horizontal lines of identical cuts. | |
| getBottomPlateYMax (self) | |
| getBottomPlateLeftCutXMin (self) | |
| getBottomPlateLeftCutYMin (self) | |
| getBottomPlateLeftCutYMax (self) | |
| getBottomPlateRightCutXMin (self) | |
| getBottomPlateRightCutYMin (self) | |
| getBottomPlateRightCutYMax (self) | |
| getBotPlateLeftRLayerXMax (self) | |
| getBottomPlateRightCutYCenter (self) | |
| getBotPlateLeftRLayerXMin (self) | |
| getBotPlateRLayerYMin (self) | |
| getBotPlateRLayerYMax (self) | |
| getBotPlateRLayerWidth (self) | |
| getBotPlateRightRLayerXCenter (self) | |
| getBotPlateLeftRLayerXCenter (self) | |
| getTopPlateRLayerYMin (self) | |
| getTopPlateRLayerYMax (self) | |
| getTopPlateRLayerWidth (self) | |
| getTopPlateRLayerXCenter (self) | |
| getTopPlateRLayerXMin (self) | |
| getTopPlateRLayerXMax (self) | |
Route two matched capacitors, C1 and C2, drawn in a capacitor matrix.
Connections are put in place with reference to a given matching scheme. Elementary capacitor units are connected to horizontal and vertical routing tracks that represent top plates and bottom plates nets of C1 and C2. Supported types of capacitors are Poly-Poly and Metal-Metal. Technologycal rules are provided by 350 nm AMS CMOS technology with three-four metal layers. Metal layers that are used for routeing are placed similarly to horziontal-vertical (HV) symbolic Alliance CAD tool router, where horizontal metal channels are drawn in metal 2 and the vertical ones are in metal 3. Given a matrix of dimensions 


An elementary capacitor unit can be a part of C1 or C2 according to the matching scheme. However, to respect common-centroid layout specifications, for C1 and C2 to be equal, the matrix number of colums and number of rows must be both even. Addionnally, the number of elementary capacitors dedicated to C1 must be equal to those dedicated to C2. These two conditions are tested in one of the class methods. An exception is raised if at least one of the two is not respected.
| __init__ | ( | self, | |
| device, | |||
| capacitance, | |||
| capacitorType = False ) |
This is the class constructor.
Basically, the class there are three categories of attributes. There are the ones related to the capacitor caracteristics, its type, dimensions. Also, there are attributes to parametrize the class into matching mode or not and there are other attributes realted to the layout varibales. The class has defaut input values, thus, in this constructor, there are two "sub-constructors" according to the entered input parameters. The class attributes are :
| device | The Hurricane AMS device into which the layout is drawn. |
| capacitance | The value of the capacitor, expressed in femto Farad (fF). |
| capacitorType | Can be MIM or PIP type capacitor. |
| abutmentPosition | Refers to the abscissa (XMin) of the bottom left corner of the abutment Box. |
| abutmentBoxYMin | Refers to the ordinate (YMin) of the bottom left corner of the abutment Box. |
Except the two last arguments, all the parameters are common with the CapacitorUnit class because the CapacitorStack constructor calls the mother class constructor to create either a compact capacitor of capacitance value or rowNumber* columnNumber unity capacitors.
| rowNumber | Number of rows in the matrix of capacitors. |
| columnNumber | Number of columns in the matrix of capacitors. |
Reimplemented from CapacitorStack.
Reimplemented in RoutMatchedCapacitor.
References CapacitorStack.abutmentBox, CapacitorUnit.abutmentBox, VerticalRoutingTracks.abutmentBox, CapacitorStack.abutmentBox_spacing, RoutMatchedCapacitor.abutmentBox_spacing, VerticalRoutingTracks.abutmentBox_spacing, RoutMatchedCapacitor.capacitor, VerticalRoutingTracks.capacitor, RoutMatchedCapacitor.capacitorIds, VerticalRoutingTracks.capacitorIds, VerticalRoutingTracks.capacitorInstance, CapacitorStack.capacitorsNumber, VerticalRoutingTracks.capacitorsNumber, CapacitorStack.capacitorType, RoutMatchedCapacitor.capacitorType, CapacitorUnit.capacitorType, VerticalRoutingTracks.capacitorType, CapacitorStack.device, CapacitorUnit.device, VerticalRoutingTracks.device, Stack.device, CapacitorStack.dummyElement, RoutMatchedCapacitor.dummyElement, VerticalRoutingTracks.dummyElement, CapacitorStack.dummyRing, RoutMatchedCapacitor.dummyRing, VerticalRoutingTracks.dummyRing, RoutMatchedCapacitor.hRoutingTrack_width, VerticalRoutingTracks.hRoutingTrack_width, CapacitorStack.matchingScheme, RoutMatchedCapacitor.matchingScheme, VerticalRoutingTracks.matchingScheme, CapacitorStack.matrixDim, RoutMatchedCapacitor.matrixDim, VerticalRoutingTracks.matrixDim, VerticalRoutingTracks.minimizeVRT, CapacitorStack.nets, RoutMatchedCapacitor.nets, VerticalRoutingTracks.nets, VerticalRoutingTracks.platesDistribution, CapacitorStack.vRoutingTrack_width, VerticalRoutingTracks.vRoutingTrack_width, RoutMatchedCapacitor.vRoutingTrackDict, VerticalRoutingTracks.vRoutingTrackDict, RoutMatchedCapacitor.vRoutingTrackXCenter, VerticalRoutingTracks.vRoutingTrackXCenter, RoutMatchedCapacitor.vRTsDistribution, VerticalRoutingTracks.vRTsDistribution, and VerticalRoutingTracks.vRTsToEliminate.
| __setStretching__ | ( | self | ) |
Sets vertical stretching value considering spacing between elementary capacitors in the matrix.
References CapacitorStack.abutmentBox_spacing, RoutMatchedCapacitor.abutmentBox_spacing, and VerticalRoutingTracks.abutmentBox_spacing.
Referenced by RoutMatchedCapacitor.computeHRLayerYCenter(), and VerticalRoutingTracks.drawVRoutingTracks().
| setRules | ( | self | ) |
Defines technology rules used to draw the layout.
Some of the rules, namely those describing routeing layers and tracks are applicable for both MIM and PIP capacitors. However, cuts rules are different.
CapacitorStack class rules are also reloaded in this class. An exception is raised if the entered capacitor type is unsupported. Reimplemented from CapacitorStack.
Reimplemented in RoutMatchedCapacitor.
References VerticalRoutingTracks.minEnclosure_hRoutingLayer_vRoutingTrack_cut, VerticalRoutingTracks.minEnclosure_hRoutingTrackCut, RoutMatchedCapacitor.minSpacing_hRoutingTrack, VerticalRoutingTracks.minSpacing_hRoutingTrack, VerticalRoutingTracks.minWidth_hRoutingLayer, RoutMatchedCapacitor.minWidth_hRoutingLayer_vRoutingTrack_cut, VerticalRoutingTracks.minWidth_hRoutingLayer_vRoutingTrack_cut, VerticalRoutingTracks.minWidth_hRoutingTrack, RoutMatchedCapacitor.minWidth_hRoutingTrackCut, and VerticalRoutingTracks.minWidth_hRoutingTrackCut.
Referenced by CapacitorStack.create(), CapacitorUnit.create(), VerticalRoutingTracks.create(), and RoutMatchedCapacitor.route().
| create | ( | self | ) |
Draw the compact or matrix of capacitors.
First, . Second, . Finally, .
Reimplemented from CapacitorStack.
References VerticalRoutingTracks.capacitorInstance, CapacitorStack.capacitorsNumber, VerticalRoutingTracks.capacitorsNumber, VerticalRoutingTracks.computeVRTDimensions(), VerticalRoutingTracks.drawVRoutingTracks(), VerticalRoutingTracks.minimizeVRTs(), CapacitorStack.setRules(), RoutMatchedCapacitor.setRules(), CapacitorUnit.setRules(), and VerticalRoutingTracks.setRules().
| drawVRoutingTracks | ( | self, | |
| vRoutingTracksLayer ) |
Iteratively draws vertical routing tracks given the physical layer vRoutingTracksLayer.
Every elementary capacitor is consequently positioned between four routing tracks, two from each side. Each couple of adjacent routeing tracks represent top plate and bottom plate nets of Ci, where i is in [1,2]. As given in Figure 2, capacitor 
References VerticalRoutingTracks.__computeVRTsNumber__(), VerticalRoutingTracks.__findCapIdsToEliminate__(), VerticalRoutingTracks.__findCapIdsToEliminatePerColumn__(), VerticalRoutingTracks.__findUsedCapIdsPerColumn__(), VerticalRoutingTracks.__findVRTsToEliminate__(), VerticalRoutingTracks.__setNetsDistribution__(), VerticalRoutingTracks.__setPlatesDistribution__(), VerticalRoutingTracks.__setStretching__(), VerticalRoutingTracks.__setVRTsDistribution__(), CapacitorStack.abutmentBox, CapacitorUnit.abutmentBox, VerticalRoutingTracks.abutmentBox, CapacitorStack.abutmentBox_spacing, RoutMatchedCapacitor.abutmentBox_spacing, VerticalRoutingTracks.abutmentBox_spacing, RoutMatchedCapacitor.capacitorIds, VerticalRoutingTracks.capacitorIds, VerticalRoutingTracks.capacitorInstance, CapacitorStack.capacitorsNumber, VerticalRoutingTracks.capacitorsNumber, VerticalRoutingTracks.computeXCenters(), CapacitorStack.dummyElement, RoutMatchedCapacitor.dummyElement, VerticalRoutingTracks.dummyElement, CapacitorStack.dummyRing, RoutMatchedCapacitor.dummyRing, VerticalRoutingTracks.dummyRing, VerticalRoutingTracks.getVTrackYMax(), VerticalRoutingTracks.getVTrackYMin(), CapacitorUnit.hpitch, RoutMatchedCapacitor.hRoutingTrack_width, VerticalRoutingTracks.hRoutingTrack_width, CapacitorStack.matchingScheme, RoutMatchedCapacitor.matchingScheme, VerticalRoutingTracks.matchingScheme, CapacitorStack.matrixDim, RoutMatchedCapacitor.matrixDim, VerticalRoutingTracks.matrixDim, RoutMatchedCapacitor.maximumPosition, VerticalRoutingTracks.maximumPosition, VerticalRoutingTracks.minEnclosure_hRoutingTrackCut, VerticalRoutingTracks.minimizeVRT, RoutMatchedCapacitor.minimumPosition, VerticalRoutingTracks.minimumPosition, VerticalRoutingTracks.minWidth_hRoutingTrack, RoutMatchedCapacitor.minWidth_hRoutingTrackCut, VerticalRoutingTracks.minWidth_hRoutingTrackCut, CapacitorStack.nets, RoutMatchedCapacitor.nets, VerticalRoutingTracks.nets, VerticalRoutingTracks.platesDistribution, CapacitorStack.vRoutingTrack_width, VerticalRoutingTracks.vRoutingTrack_width, RoutMatchedCapacitor.vRoutingTrackDict, VerticalRoutingTracks.vRoutingTrackDict, RoutMatchedCapacitor.vRoutingTrackXCenter, VerticalRoutingTracks.vRoutingTrackXCenter, RoutMatchedCapacitor.vRTsDistribution, VerticalRoutingTracks.vRTsDistribution, and VerticalRoutingTracks.vRTsToEliminate.
Referenced by VerticalRoutingTracks.create().
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