21 #ifndef GNSS_SDR_FMCOMMS5_SIGNAL_SOURCE_FPGA_H 22 #define GNSS_SDR_FMCOMMS5_SIGNAL_SOURCE_FPGA_H 50 const std::string &role,
unsigned int in_stream,
55 inline size_t item_size()
override 60 void connect(gr::top_block_sptr top_block)
override;
61 void disconnect(gr::top_block_sptr top_block)
override;
62 gr::basic_block_sptr get_left_block()
override;
63 gr::basic_block_sptr get_right_block()
override;
66 const std::string default_dump_filename = std::string(
"FPGA_buffer_monitor_dump.dat");
67 const std::string default_rf_port_select = std::string(
"A_BALANCED");
68 const std::string default_gain_mode = std::string(
"slow_attack");
69 const double default_manual_gain_rx1 = 64.0;
70 const double default_manual_gain_rx2 = 64.0;
71 const uint64_t default_bandwidth = 12500000;
74 const uint32_t Gain_control_period_ms = 500;
76 const uint32_t buffer_monitor_period_ms = 1000;
78 const uint32_t buffer_monitoring_initial_delay_ms = 2000;
79 const int32_t switch_to_real_time_mode = 2;
81 void run_dynamic_bit_selection_process();
82 void run_buffer_monitor_process();
84 mutable std::mutex dynamic_bit_selection_mutex;
85 mutable std::mutex buffer_monitor_mutex;
87 std::thread thread_dynamic_bit_selection;
88 std::thread thread_buffer_monitor;
90 std::shared_ptr<Fpga_Switch> switch_fpga;
91 std::shared_ptr<Fpga_dynamic_bit_selection> dynamic_bit_selection_fpga;
92 std::shared_ptr<Fpga_buffer_monitor> buffer_monitor_fpga;
94 std::string gain_mode_rx1_;
95 std::string gain_mode_rx2_;
96 std::string rf_port_select_;
97 std::string filter_file_;
98 std::string filter_source_;
99 std::string filter_filename_;
106 uint64_t sample_rate_;
112 uint32_t out_stream_;
121 bool enable_dynamic_bit_selection_;
122 bool enable_ovf_check_buffer_monitor_active_;
130 #endif // GNSS_SDR_FMCOMMS5_SIGNAL_SOURCE_FPGA_H Interface of a thread-safe std::queue.
Header file of the base class to signal_source GNSS blocks.
Check receiver buffer overflow and monitor the status of the receiver buffers.
This interface represents a GNSS block.
This abstract class represents an interface to configuration parameters.
Switch that connects the HW accelerator queues to the analog front end or the DMA.
Dynamic bit selection in the received signal.