rtl2832-tuner_e4k.h

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#ifndef _E4K_TUNER_H
#define _E4K_TUNER_H

#include "rtl2832.h"

namespace RTL2832_NAMESPACE { namespace TUNERS_NAMESPACE {

class e4k;

} } // TUNERS_NAMESPACE // RTL2832_NAMESPACE

///////////////////////////////////////////////////////////////////////////////

/* (C) 2011-2012 by Harald Welte <laforge@gnumonks.org>
 *
 * All Rights Reserved
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

enum e4k_reg {
        E4K_REG_MASTER1         = 0x00,
        E4K_REG_MASTER2         = 0x01,
        E4K_REG_MASTER3         = 0x02,
        E4K_REG_MASTER4         = 0x03,
        E4K_REG_MASTER5         = 0x04,
        E4K_REG_CLK_INP         = 0x05,
        E4K_REG_REF_CLK         = 0x06,
        E4K_REG_SYNTH1          = 0x07,
        E4K_REG_SYNTH2          = 0x08,
        E4K_REG_SYNTH3          = 0x09,
        E4K_REG_SYNTH4          = 0x0a,
        E4K_REG_SYNTH5          = 0x0b,
        E4K_REG_SYNTH6          = 0x0c,
        E4K_REG_SYNTH7          = 0x0d,
        E4K_REG_SYNTH8          = 0x0e,
        E4K_REG_SYNTH9          = 0x0f,
        E4K_REG_FILT1           = 0x10,
        E4K_REG_FILT2           = 0x11,
        E4K_REG_FILT3           = 0x12,
        // gap
        E4K_REG_GAIN1           = 0x14,
        E4K_REG_GAIN2           = 0x15,
        E4K_REG_GAIN3           = 0x16,
        E4K_REG_GAIN4           = 0x17,
        // gap
        E4K_REG_AGC1            = 0x1a,
        E4K_REG_AGC2            = 0x1b,
        E4K_REG_AGC3            = 0x1c,
        E4K_REG_AGC4            = 0x1d,
        E4K_REG_AGC5            = 0x1e,
        E4K_REG_AGC6            = 0x1f,
        E4K_REG_AGC7            = 0x20,
        E4K_REG_AGC8            = 0x21,
        // gap
        E4K_REG_AGC11           = 0x24,
        E4K_REG_AGC12           = 0x25,
        // gap
        E4K_REG_DC1             = 0x29,
        E4K_REG_DC2             = 0x2a,
        E4K_REG_DC3             = 0x2b,
        E4K_REG_DC4             = 0x2c,
        E4K_REG_DC5             = 0x2d,
        E4K_REG_DC6             = 0x2e,
        E4K_REG_DC7             = 0x2f,
        E4K_REG_DC8             = 0x30,
        // gap
        E4K_REG_QLUT0           = 0x50,
        E4K_REG_QLUT1           = 0x51,
        E4K_REG_QLUT2           = 0x52,
        E4K_REG_QLUT3           = 0x53,
        // gap
        E4K_REG_ILUT0           = 0x60,
        E4K_REG_ILUT1           = 0x61,
        E4K_REG_ILUT2           = 0x62,
        E4K_REG_ILUT3           = 0x63,
        // gap
        E4K_REG_DCTIME1         = 0x70,
        E4K_REG_DCTIME2         = 0x71,
        E4K_REG_DCTIME3         = 0x72,
        E4K_REG_DCTIME4         = 0x73,
        E4K_REG_PWM1            = 0x74,
        E4K_REG_PWM2            = 0x75,
        E4K_REG_PWM3            = 0x76,
        E4K_REG_PWM4            = 0x77,
        E4K_REG_BIAS            = 0x78,
        E4K_REG_CLKOUT_PWDN     = 0x7a,
        E4K_REG_CHFILT_CALIB    = 0x7b,
        E4K_REG_I2C_REG_ADDR    = 0x7d,
        // FIXME
};

#define E4K_MASTER1_RESET       (1 << 0)
#define E4K_MASTER1_NORM_STBY   (1 << 1)
#define E4K_MASTER1_POR_DET     (1 << 2)

#define E4K_SYNTH1_PLL_LOCK     (1 << 0)
#define E4K_SYNTH1_BAND_SHIF    1

#define E4K_SYNTH7_3PHASE_EN    (1 << 3)

#define E4K_SYNTH8_VCOCAL_UPD   (1 << 2)

#define E4K_FILT3_DISABLE       (1 << 5)

#define E4K_AGC1_LIN_MODE       (1 << 4)
#define E4K_AGC1_LNA_UPDATE     (1 << 5)
#define E4K_AGC1_LNA_G_LOW      (1 << 6)
#define E4K_AGC1_LNA_G_HIGH     (1 << 7)

#define E4K_AGC6_LNA_CAL_REQ    (1 << 4)

#define E4K_AGC7_MIX_GAIN_AUTO  (1 << 0)
#define E4K_AGC7_GAIN_STEP_5dB  (1 << 5)

#define E4K_AGC8_SENS_LIN_AUTO  (1 << 0)

#define E4K_AGC11_LNA_GAIN_ENH  (1 << 0)

#define E4K_DC1_CAL_REQ         (1 << 0)

#define E4K_DC5_I_LUT_EN        (1 << 0)
#define E4K_DC5_Q_LUT_EN        (1 << 1)
#define E4K_DC5_RANGE_DET_EN    (1 << 2)
#define E4K_DC5_RANGE_EN        (1 << 3)
#define E4K_DC5_TIMEVAR_EN      (1 << 4)

#define E4K_CLKOUT_DISABLE      0x96

#define E4K_CHFCALIB_CMD        (1 << 0)

#define E4K_AGC1_MOD_MASK       0xF

enum e4k_agc_mode {
        E4K_AGC_MOD_SERIAL              = 0x0,
        E4K_AGC_MOD_IF_PWM_LNA_SERIAL   = 0x1,
        E4K_AGC_MOD_IF_PWM_LNA_AUTONL   = 0x2,
        E4K_AGC_MOD_IF_PWM_LNA_SUPERV   = 0x3,
        E4K_AGC_MOD_IF_SERIAL_LNA_PWM   = 0x4,
        E4K_AGC_MOD_IF_PWM_LNA_PWM      = 0x5,
        E4K_AGC_MOD_IF_DIG_LNA_SERIAL   = 0x6,
        E4K_AGC_MOD_IF_DIG_LNA_AUTON    = 0x7,
        E4K_AGC_MOD_IF_DIG_LNA_SUPERV   = 0x8,
        E4K_AGC_MOD_IF_SERIAL_LNA_AUTON = 0x9,
        E4K_AGC_MOD_IF_SERIAL_LNA_SUPERV = 0xa,
};

enum e4k_band {
        E4K_BAND_VHF2   = 0,
        E4K_BAND_VHF3   = 1,
        E4K_BAND_UHF    = 2,
        E4K_BAND_L      = 3,
};

enum e4k_mixer_filter_bw {
        E4K_F_MIX_BW_27M        = 0,
        E4K_F_MIX_BW_4M6        = 8,
        E4K_F_MIX_BW_4M2        = 9,
        E4K_F_MIX_BW_3M8        = 10,
        E4K_F_MIX_BW_3M4        = 11,
        E4K_F_MIX_BW_3M         = 12,
        E4K_F_MIX_BW_2M7        = 13,
        E4K_F_MIX_BW_2M3        = 14,
        E4K_F_MIX_BW_1M9        = 15,
};

enum e4k_if_filter {
        E4K_IF_FILTER_MIX,
        E4K_IF_FILTER_CHAN,
        E4K_IF_FILTER_RC
};
struct e4k_pll_params {
        uint32_t fosc;
        uint32_t intended_flo;
        uint32_t flo;
        uint16_t x;
        uint8_t z;
        uint8_t r;
        uint8_t r_idx;
        uint8_t threephase;
};

struct e4k_state {
        RTL2832_NAMESPACE::TUNERS_NAMESPACE::e4k* pTuner;
        uint8_t i2c_addr;
        enum e4k_band band;
        struct e4k_pll_params vco;
};

///////////////////////////////////////////////////////////////////////////////

/* structure describing a field in a register */
struct reg_field {
        uint8_t reg;
        uint8_t shift;
        uint8_t width;
};

struct reg_field_ops {
        const struct reg_field *fields;
        const char **field_names;
        uint32_t num_fields;
        void *data;
        int (*write_cb)(void *data, uint32_t reg, uint32_t val);
        uint32_t (*read_cb)(void *data, uint32_t reg);
};

enum cmd_op {
        CMD_OP_GET      = (1 << 0),
        CMD_OP_SET      = (1 << 1),
        CMD_OP_EXEC     = (1 << 2),
};

uint32_t reg_field_read(struct reg_field_ops *ops, struct reg_field *field);
int reg_field_write(struct reg_field_ops *ops, struct reg_field *field, uint32_t val);
int reg_field_cmd(struct cmd_state *cs, enum cmd_op op,
                  const char *cmd, int argc, char **argv,
                  struct reg_field_ops *ops);

///////////////////////////////////////////////////////////////////////////////

int e4k_init(struct e4k_state *e4k, bool enable_dc_offset_loop = true, bool set_manual_gain = false);
int e4k_if_gain_set(struct e4k_state *e4k, uint8_t stage, int8_t value);
int e4k_mixer_gain_set(struct e4k_state *e4k, int8_t value);
int e4k_commonmode_set(struct e4k_state *e4k, int8_t value);
int e4k_tune_freq(struct e4k_state *e4k, uint32_t freq);
int e4k_tune_params(struct e4k_state *e4k, struct e4k_pll_params *p);
int e4k_compute_pll_params(struct e4k_pll_params *oscp, uint32_t fosc, uint32_t intended_flo);
int e4k_if_filter_bw_get(struct e4k_state *e4k, enum e4k_if_filter filter);
int e4k_if_filter_bw_set(struct e4k_state *e4k, enum e4k_if_filter filter,
                         uint32_t bandwidth);
int e4k_if_filter_chan_enable(struct e4k_state *e4k, int on);
int e4k_rf_filter_set(struct e4k_state *e4k);
/*
int e4k_reg_write(struct e4k_state *e4k, uint8_t reg, uint8_t val);
int e4k_reg_read(struct e4k_state *e4k, uint8_t reg);
*/
int sam3u_e4k_init(struct e4k_state *e4k, void *i2c, uint8_t slave_addr);
void sam3u_e4k_power(struct e4k_state *e4k, int on);
void sam3u_e4k_stby(struct e4k_state *e4k, int on);


int e4k_manual_dc_offset(struct e4k_state *e4k, int8_t iofs, int8_t irange, int8_t qofs, int8_t qrange);
int e4k_dc_offset_calibrate(struct e4k_state *e4k);
int e4k_dc_offset_gen_table(struct e4k_state *e4k);

///////////////////////////////////////////////////////////////////////////////

namespace RTL2832_NAMESPACE { namespace TUNERS_NAMESPACE {

class e4k : public RTL2832_NAMESPACE::tuner_skeleton
{
IMPLEMENT_INLINE_TUNER_FACTORY(e4k)
public:
        e4k(demod* p);
public:
        inline virtual const char* name() const
        { return "Elonics E4K"; }
public:
        int initialise(tuner::PPARAMS params = NULL);
        int set_frequency(double freq);
        int set_bandwidth(double bw);
        int set_gain(double gain);
        int set_gain_mode(int mode);
        int set_auto_gain_mode(bool on = true);
        bool calc_appropriate_gain_mode(int& mode)/* const*/;
private:
        int update_gain_mode();
public:
        struct e4k_state m_stateE4K;
};

} } // TUNERS_NAMESPACE, RTL2832_NAMESPACE

///////////////////////////////////////////////////////////////////////////////

#define RTL2832_E4000_ADDITIONAL_INIT_REG_TABLE_LEN             34

#define RTL2832_E4000_LNA_GAIN_TABLE_LEN                                16
#define RTL2832_E4000_LNA_GAIN_ADD_TABLE_LEN                    8
#define RTL2832_E4000_MIXER_GAIN_TABLE_LEN                              2
#define RTL2832_E4000_IF_STAGE_1_GAIN_TABLE_LEN                 2
#define RTL2832_E4000_IF_STAGE_2_GAIN_TABLE_LEN                 4
#define RTL2832_E4000_IF_STAGE_3_GAIN_TABLE_LEN                 4
#define RTL2832_E4000_IF_STAGE_4_GAIN_TABLE_LEN                 4
#define RTL2832_E4000_IF_STAGE_5_GAIN_TABLE_LEN                 8
#define RTL2832_E4000_IF_STAGE_6_GAIN_TABLE_LEN                 8

#define RTL2832_E4000_LNA_GAIN_BAND_NUM                                 2
#define RTL2832_E4000_MIXER_GAIN_BAND_NUM                               2

#define RTL2832_E4000_RF_BAND_BOUNDARY_HZ                               300000000

#define RTL2832_E4000_LNA_GAIN_ADDR                                             0x14
#define RTL2832_E4000_LNA_GAIN_MASK                                             0xf
#define RTL2832_E4000_LNA_GAIN_SHIFT                                    0

#define RTL2832_E4000_LNA_GAIN_ADD_ADDR                                 0x24
#define RTL2832_E4000_LNA_GAIN_ADD_MASK                                 0x7
#define RTL2832_E4000_LNA_GAIN_ADD_SHIFT                                0

#define RTL2832_E4000_MIXER_GAIN_ADDR                                   0x15
#define RTL2832_E4000_MIXER_GAIN_MASK                                   0x1
#define RTL2832_E4000_MIXER_GAIN_SHIFT                                  0

#define RTL2832_E4000_IF_STAGE_1_GAIN_ADDR                              0x16
#define RTL2832_E4000_IF_STAGE_1_GAIN_MASK                              0x1
#define RTL2832_E4000_IF_STAGE_1_GAIN_SHIFT                             0

#define RTL2832_E4000_IF_STAGE_2_GAIN_ADDR                              0x16
#define RTL2832_E4000_IF_STAGE_2_GAIN_MASK                              0x6
#define RTL2832_E4000_IF_STAGE_2_GAIN_SHIFT                             1

#define RTL2832_E4000_IF_STAGE_3_GAIN_ADDR                              0x16
#define RTL2832_E4000_IF_STAGE_3_GAIN_MASK                              0x18
#define RTL2832_E4000_IF_STAGE_3_GAIN_SHIFT                             3

#define RTL2832_E4000_IF_STAGE_4_GAIN_ADDR                              0x16
#define RTL2832_E4000_IF_STAGE_4_GAIN_MASK                              0x60
#define RTL2832_E4000_IF_STAGE_4_GAIN_SHIFT                             5

#define RTL2832_E4000_IF_STAGE_5_GAIN_ADDR                              0x17
#define RTL2832_E4000_IF_STAGE_5_GAIN_MASK                              0x7
#define RTL2832_E4000_IF_STAGE_5_GAIN_SHIFT                             0

#define RTL2832_E4000_IF_STAGE_6_GAIN_ADDR                              0x17
#define RTL2832_E4000_IF_STAGE_6_GAIN_MASK                              0x38
#define RTL2832_E4000_IF_STAGE_6_GAIN_SHIFT                             3

#define RTL2832_E4000_TUNER_OUTPUT_POWER_UNIT_0P1_DBM   -100

#define RTL2832_E4000_TUNER_MODE_UPDATE_WAIT_TIME_MS    1000

#endif /* _E4K_TUNER_H */