GNU Radio's HOWTO Package
usrp_commands.h
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1 /*
2  * USRP - Universal Software Radio Peripheral
3  *
4  * Copyright (C) 2003,2004 Free Software Foundation, Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19  */
20 
21 #ifndef _USRP_COMMANDS_H_
22 #define _USRP_COMMANDS_H_
23 
24 
25 #define MAX_EP0_PKTSIZE 64 // max size of EP0 packet on FX2
26 
27 // ----------------------------------------------------------------
28 // Vendor bmRequestType's
29 // ----------------------------------------------------------------
30 
31 #define VRT_VENDOR_IN 0xC0
32 #define VRT_VENDOR_OUT 0x40
33 
34 // ----------------------------------------------------------------
35 // USRP Vendor Requests
36 //
37 // Note that Cypress reserves [0xA0,0xAF].
38 // 0xA0 is the firmware load function.
39 // ----------------------------------------------------------------
40 
41 
42 // IN commands
43 
44 #define VRQ_GET_STATUS 0x80
45 #define GS_TX_UNDERRUN 0 // wIndexL // returns 1 byte
46 #define GS_RX_OVERRUN 1 // wIndexL // returns 1 byte
47 
48 #define VRQ_I2C_READ 0x81 // wValueL: i2c address; length: how much to read
49 
50 #define VRQ_SPI_READ 0x82 // wValue: optional header bytes
51  // wIndexH: enables
52  // wIndexL: format
53  // len: how much to read
54 
55 // OUT commands
56 
57 #define VRQ_SET_LED 0x01 // wValueL off/on {0,1}; wIndexL: which {0,1}
58 
59 #define VRQ_FPGA_LOAD 0x02
60 # define FL_BEGIN 0 // wIndexL: begin fpga programming cycle. stalls if trouble.
61 # define FL_XFER 1 // wIndexL: xfer up to 64 bytes of data
62 # define FL_END 2 // wIndexL: end programming cycle, check for success.
63  // stalls endpoint if trouble.
64 
65 #define VRQ_FPGA_WRITE_REG 0x03 // wIndexL: regno; data: 32-bit regval MSB first
66 #define VRQ_FPGA_SET_RESET 0x04 // wValueL: {0,1}
67 #define VRQ_FPGA_SET_TX_ENABLE 0x05 // wValueL: {0,1}
68 #define VRQ_FPGA_SET_RX_ENABLE 0x06 // wValueL: {0,1}
69 // see below VRQ_FPGA_SET_{TX,RX}_RESET
70 
71 #define VRQ_SET_SLEEP_BITS 0x07 // wValueH: mask; wValueL: bits. set bits given by mask to bits
72 
73 # define SLEEP_ADC0 0x01
74 # define SLEEP_ADC1 0x02
75 # define SLEEP_DAC0 0x04
76 # define SLEEP_DAC1 0x08
77 
78 #define VRQ_I2C_WRITE 0x08 // wValueL: i2c address; data: data
79 
80 #define VRQ_SPI_WRITE 0x09 // wValue: optional header bytes
81  // wIndexH: enables
82  // wIndexL: format
83  // len: how much to write
84 
85 #define VRQ_FPGA_SET_TX_RESET 0x0a // wValueL: {0, 1}
86 #define VRQ_FPGA_SET_RX_RESET 0x0b // wValueL: {0, 1}
87 
88 
89 // -------------------------------------------------------------------
90 // we store the hashes at fixed addresses in the FX2 internal memory
91 
92 #define USRP_HASH_SLOT_0_ADDR 0xe1e0
93 #define USRP_HASH_SLOT_1_ADDR 0xe1f0
94 
95 
96 
97 #endif /* _USRP_COMMANDS_H_ */