GNSS-SDR 0.0.21
An Open Source GNSS Software Defined Receiver
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base_pcps_acquisition_fpga.h
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1/*!
2 * \file base_pcps_acquisition_fpga.h
3 * \brief Shared implementation for FPGA-based PCPS acquisition adapters
4 * \authors Carles Fernandez, 2025. carles.fernandez(at)cttc.cat
5 *
6 * -----------------------------------------------------------------------------
7 *
8 * GNSS-SDR is a Global Navigation Satellite System software-defined receiver.
9 * This file is part of GNSS-SDR.
10 *
11 * Copyright (C) 2010-2025 (see AUTHORS file for a list of contributors)
12 * SPDX-License-Identifier: GPL-3.0-or-later
13 *
14 * -----------------------------------------------------------------------------
15 */
16
17
18#ifndef GNSS_SDR_BASE_PCPS_ACQUISITION_FPGA_H
19#define GNSS_SDR_BASE_PCPS_ACQUISITION_FPGA_H
20
21#include "acq_conf_fpga.h"
22#include "channel_fsm.h"
23#include "gnss_synchro.h"
25#include <gnuradio/runtime_types.h> // for basic_block_sptr, top_block_sptr
26#include <volk_gnsssdr/volk_gnsssdr_alloc.h>
27#include <cstddef>
28#include <cstdint>
29#include <memory>
30#include <string>
31
32/** \addtogroup Acquisition
33 * Classes for GNSS signal acquisition
34 * \{ */
35/** \addtogroup Acq_adapters acquisition_adapters
36 * Wrap GNU Radio acquisition blocks with an AcquisitionInterface
37 * \{ */
38
40
41/*!
42 * \brief Base class providing shared logic for FPGA-based GPS PCPS acquisition adapters.
43 */
44class BasePcpsAcquisitionFpga : public AcquisitionInterface
45{
46public:
47 BasePcpsAcquisitionFpga(const ConfigurationInterface* configuration,
48 std::string role,
49 double code_rate_cps,
50 double code_length_chips,
51 uint32_t opt_acq_fs_sps,
52 uint32_t default_fpga_blk_exp,
53 uint32_t acq_buff,
54 unsigned int in_streams,
55 unsigned int out_streams);
56
57 ~BasePcpsAcquisitionFpga() override = default;
58
59 inline std::string role() override final { return role_; }
60
61 inline size_t item_size() override { return sizeof(int16_t); }
62
63 // Common AcquisitionInterface overrides
64 void connect(gr::top_block_sptr top_block) override;
65 void disconnect(gr::top_block_sptr top_block) override;
66 gr::basic_block_sptr get_left_block() override;
67 gr::basic_block_sptr get_right_block() override;
68
69 signed int mag() override;
70 void set_gnss_synchro(Gnss_Synchro* p_gnss_synchro) override;
71 void set_channel(unsigned int channel) override;
72 void set_channel_fsm(std::weak_ptr<ChannelFsm> channel_fsm) override;
73 void set_doppler_center(int doppler_center) override;
74 void reset() override;
75 void stop_acquisition() override;
76 void set_resampler_latency(uint32_t latency_samples __attribute__((unused))) override {}
77 void set_local_code() override;
78
79protected:
80 // Members subclasses can use
81 static const uint32_t QUANT_BITS_LOCAL_CODE = 16;
82 static const uint32_t SELECT_LSBITS = 0x0000FFFF; // Select the 10 LSbits out of a 20-bit word
83 static const uint32_t SELECT_MSBITS = 0xFFFF0000; // Select the 10 MSbits out of a 20-bit word
84 static const uint32_t SELECT_ALL_CODE_BITS = 0xFFFFFFFF; // Select a 20 bit word
85 static const uint32_t SHL_CODE_BITS = 65536; // shift left by 10 bits
86 static const uint32_t ACQ_BUFF_0 = 0; // FPGA Acquisition IP buffer containing L1/E1 frequency band samples by default.
87 static const uint32_t ACQ_BUFF_1 = 1; // FPGA Acquisition IP buffer containing L2 or L5/E5 frequency band samples by default.
88
89 // parameter initialization
90 void init();
91
92 // Members subclasses must set
93 volk_gnsssdr::vector<uint32_t> d_all_fft_codes_;
94 Acq_Conf_Fpga acq_parameters_;
95
96private:
97 // Managed entirely by the base class
98 pcps_acquisition_fpga_sptr acquisition_fpga_;
99 const std::string role_;
100};
101
102
103/** \} */
104/** \} */
105#endif // GNSS_SDR_BASE_PCPS_ACQUISITION_FPGA_H
Class that contains all the configuration parameters for generic acquisition block based on the PCPS ...
Interface of the State Machine for channel.
This abstract class represents an interface to an acquisition GNSS block.
This abstract class represents an interface to configuration parameters.
This is the class that contains the information that is shared by the processing blocks.
Interface of the Gnss_Synchro class.
This class implements a Parallel Code Phase Search Acquisition for the FPGA.